Abstract: An integrated circuit may include a bit cell array including a plurality of bit cells and a peripheral region including a peripheral circuit. The peripheral region may include a plurality of devices over a substrate, at least one pattern configured to provide a first voltage to at least one of the plurality of devices, at least one power line extending under the substrate, and at least one first via passing through the substrate in a vertical direction in the peripheral region and electrically connecting the at least one pattern to the at least one power line.

Abstract: An integrated circuit includes: a dual port Static Random Access Memory (SRAM) cell including a plurality of transistors; a bit line pair connected to the dual port SRAM cell, the bit line pair including a first bit line and a second bit line spaced apart from each other in a first direction and extending in a second direction perpendicular to the first direction; a power line group including a plurality of power lines spaced apart from each other in the first direction, spaced apart from the bit line pair placed in the first direction, and extending in the second direction, the power line group being configured to apply a voltage to the dual-port SRAM cell; and a first word line provided between the first bit line and the second bit line and connected to the dual port SRAM cell.

Abstract: An integrated circuit includes: a dual port Static Random Access Memory (SRAM) cell including a plurality of transistors; a bit line pair connected to the dual port SRAM cell, the bit line pair including a first bit line and a second bit line spaced apart from each other in a first direction and extending in a second direction perpendicular to the first direction; a power line group including a plurality of power lines spaced apart from each other in the first direction, spaced apart from the bit line pair placed in the first direction, and extending in the second direction, the power line group being configured to apply a voltage to the dual-port SRAM cell; and a first word line provided between the first bit line and the second bit line and connected to the dual port SRAM cell.

Abstract: A semiconductor device includes a first memory column group including a plurality of memory columns in which a plurality of bit cells are disposed; and a first peripheral column group including a plurality of peripheral columns in which a plurality of standard cells are disposed, wherein the plurality of standard cells are configured to perform an operation of reading/writing data from/to the plurality of bit cells through a plurality of bit lines, wherein the first memory column group and the first peripheral column group correspond to each other in a column direction, and wherein at least one of the plurality of peripheral columns has a cell height different from cell heights of the other peripheral columns, the cell height being measured in a row direction in which a gate line is extended.

Abstract: An integrated circuit includes: a memory cell block including a plurality of bitcells; and an input and output (I/O) block including a plurality of gate-all-around (GAA) transistors connected to the bitcells, wherein the I/O block includes a plurality of active regions disposed separately from one another in a first direction, each of which extends in a second direction that is vertical to the first direction, and in which the GAA transistors are formed, a plurality of power rails disposed separately from one another in the first direction, and configured to provide power to the GAA transistors, and a plurality of signal lines disposed between the power rails, and configured to provide signals to the GAA transistors, a first number of bitcells among the bitcells are connected to the GAA transistors formed in a second number of active regions among the active regions, and the second number is twice the first number.

Abstract: A semiconductor device including memory cell transistors on a substrate is provided. The semiconductor device includes a first wiring layer on the memory cell transistors and including a bit line and a first conductive pattern, a second wiring layer on the first wiring layer and including a ground line, a first via interposed between and electrically connecting the bit line and a source/drain of a first memory cell transistor among the memory cell transistors, and a first extended via interposed between the ground line and a source/drain of a second memory cell transistor among the memory cell transistors. The ground line is electrically connected to the source/drain of the second memory cell transistor through the first extended via and the first conductive pattern. The first extended via has a width greater than that of the first via.

Abstract: A memory device includes a first write assist circuit providing a cell voltage or a write assist voltage to a first memory cell connected with a first bit line pair, a first write driver that provides write data to the first memory cell through the first bit line pair, a second write assist circuit that provides the cell voltage or the write assist voltage to a second memory cell connected with a second bit line pair, and a second write driver that provides write data to the second memory cell through the second bit line pair. One of the first and second write assist circuits provides the write assist voltage in response to a column selection signal for selecting one write driver, which provides write data, from among the first, and second write drivers, and the other thereof provides the cell voltage in response to the column selection signal.

Abstract: A semiconductor device including memory cell transistors on a substrate is provided. The semiconductor device includes a first wiring layer on the memory cell transistors and including a bit line and a first conductive pattern, a second wiring layer on the first wiring layer and including a ground line, a first via interposed between and electrically connecting the bit line and a source/drain of a first memory cell transistor among the memory cell transistors, and a first extended via interposed between the ground line and a source/drain of a second memory cell transistor among the memory cell transistors. The ground line is electrically connected to the source/drain of the second memory cell transistor through the first extended via and the first conductive pattern. The first extended via has a width greater than that of the first via.

Abstract: A semiconductor device including memory cell transistors on a substrate is provided. The semiconductor device includes a first wiring layer on the memory cell transistors and including a bit line and a first conductive pattern, a second wiring layer on the first wiring layer and including a ground line, a first via interposed between and electrically connecting the bit line and a source/drain of a first memory cell transistor among the memory cell transistors, and a first extended via interposed between the ground line and a source/drain of a second memory cell transistor among the memory cell transistors. The ground line is electrically connected to the source/drain of the second memory cell transistor through the first extended via and the first conductive pattern. The first extended via has a width greater than that of the first via.

Abstract: A memory device includes a first write assist circuit providing a cell voltage or a write assist voltage to a first memory cell connected with a first bit line pair, a first write driver that provides write data to the first memory cell through the first bit line pair, a second write assist circuit that provides the cell voltage or the write assist voltage to a second memory cell connected with a second bit line pair, and a second write driver that provides write data to the second memory cell through the second bit line pair. One of the first and second write assist circuits provides the write assist voltage in response to a column selection signal for selecting one write driver, which provides write data, from among the first, and second write drivers, and the other thereof provides the cell voltage in response to the column selection signal.

Abstract: A semiconductor device including memory cell transistors on a substrate is provided. The semiconductor device includes a first wiring layer on the memory cell transistors and including a bit line and a first conductive pattern, a second wiring layer on the first wiring layer and including a ground line, a first via interposed between and electrically connecting the bit line and a source/drain of a first memory cell transistor among the memory cell transistors, and a first extended via interposed between the ground line and a source/drain of a second memory cell transistor among the memory cell transistors. The ground line is electrically connected to the source/drain of the second memory cell transistor through the first extended via and the first conductive pattern. The first extended via has a width greater than that of the first via.

Abstract: Integrated circuit devices include a substrate having a semiconductor substrate region therein containing multiple well regions of different conductivity type. A first semiconductor well region of first conductivity type is provided in the semiconductor substrate region. This first semiconductor well region has a first plurality of transistor regions therein arranged in a first zig-zag pattern extending across the semiconductor substrate region. A second semiconductor well region of second conductivity type is also provided in the semiconductor substrate region. This second semiconductor well region has a second plurality of transistor regions therein arranged in a second zig-zag pattern extending across the semiconductor substrate region. This second zig-zag pattern is intertwined with the first zig-zag pattern.

Abstract: Integrated circuit devices include a substrate having a semiconductor substrate region therein containing multiple well regions of different conductivity type. A first semiconductor well region of first conductivity type is provided in the semiconductor substrate region. This first semiconductor well region has a first plurality of transistor regions therein arranged in a first zig-zag pattern extending across the semiconductor substrate region. A second semiconductor well region of second conductivity type is also provided in the semiconductor substrate region. This second semiconductor well region has a second plurality of transistor regions therein arranged in a second zig-zag pattern extending across the semiconductor substrate region. This second zig-zag pattern is intertwined with the first zig-zag pattern.