Abstract: A semiconductor device including a first conductive layer on a substrate, a second conductive layer on the first conductive layer, a contact structure between the first and second conductive layers, and a barrier structure surrounding a lower region of a side surface of the second conductive layer, wherein the contact structure includes a contact conductive layer having a first upper surface portion and a second upper surface extending from the first upper surface portion and being concave, and a gap-fill pattern fills a space between the second upper surface portion and the second conductive layer and includes a first gap-fill insulating layer including a metal element and a second gap-fill insulating layer including a silicon element, and the barrier structure includes a first etch stop layer and a barrier layer that include same materials as the first insulating material and the second insulating material, respectively, may be provided.

Abstract: A method of fabricating a semiconductor device is disclosed. The method may include forming an etch-target layer, a mask layer, a blocking layer, and a photoresist layer, which are sequentially stacked on a substrate; forming a photoresist pattern, the forming the photoresist pattern including irradiating the photoresist layer with extreme ultraviolet (EUV) light; forming a mask layer, the forming the mask layer including etching the mask layer using the photoresist pattern as an etch mask; and forming a target pattern, the forming the target pattern including etching the etch-target layer using the mask pattern as an etch mask. The photoresist layer may include an organic metal oxide. The blocking layer may be a non-polar layer and may limit and/or prevent a metallic element in the photoresist layer from infiltrating into the mask layer.

Abstract: A semiconductor device includes a substrate having an active region, a first insulating layer on the substrate, a second insulating layer on the first insulating layer, an etch stop layer between the first insulating layer and the second insulating layer, a via contact in the first insulating layer and electrically connected to the active region, an interconnection electrode in the second insulating layer and electrically connected to the via contact, a conductive barrier layer on a side surface and a lower surface of the interconnection electrode and having an extension portion extending to a partial region of a side surface of the via contact, and a side insulating layer on a side region of the via contact below the extension portion of the conductive barrier layer, the side insulating layer including the same material as a material of the etch stop layer.

Abstract: A semiconductor device is provided. The semiconductor device includes first metal lines on a lower layer, a dielectric barrier layer provided on the lower layer to cover side and top surfaces of the first metal lines, an etch stop layer provided on the dielectric barrier layer to define gap regions between the first metal lines, an upper insulating layer on the etch stop layer, and a conductive via penetrating the upper insulating layer, the etch stop layer, and the dielectric barrier layer to contact a top surface of a first metal line. The etch stop layer includes first portions on the first metal lines and second portions between the first metal lines. The second portions of the etch stop layer are higher than the first portions.

Abstract: A semiconductor device comprises a lower structure on a substrate and including a recess region, first and second barrier layers covering an inner surface of the recess region and a top surface of the lower structure, the inner surface of the recess region including a bottom surface and an inner sidewall connecting the bottom surface to the top surface of the lower structure, and an interlayer dielectric layer provided on the second barrier layer and defining an air gap in the recess region. A first step coverage is obtained by dividing a thickness of the first barrier layer on an inner sidewall of the recess region by a thickness of the first barrier layer on the top surface of the lower structure. A second step coverage is obtained by dividing a thickness of the second barrier layer on the inner sidewall of the recess region by a thickness of the second barrier layer on the top surface of the lower structure. The first step coverage is different from the second step coverage.

Abstract: A semiconductor device is provided. The semiconductor device includes first metal lines on a lower layer, a dielectric barrier layer provided on the lower layer to cover side and top surfaces of the first metal lines, an etch stop layer provided on the dielectric barrier layer to define gap regions between the first metal lines, an upper insulating layer on the etch stop layer, and a conductive via penetrating the upper insulating layer, the etch stop layer, and the dielectric barrier layer to contact a top surface of a first metal line. The etch stop layer includes first portions on the first metal lines and second portions between the first metal lines. The second portions of the etch stop layer are higher than the first portions.

Abstract: A semiconductor device comprises a lower structure on a substrate and including a recess region, first and second barrier layers covering an inner surface of the recess region and a top surface of the lower structure, the inner surface of the recess region including a bottom surface and an inner sidewall connecting the bottom surface to the top surface of the lower structure, and an interlayer dielectric layer provided on the second barrier layer and defining an air gap in the recess region. A first step coverage is obtained by dividing a thickness of the first barrier layer on an inner sidewall of the recess region by a thickness of the first barrier layer on the top surface of the lower structure. A second step coverage is obtained by dividing a thickness of the second barrier layer on the inner sidewall of the recess region by a thickness of the second barrier layer on the top surface of the lower structure. The first step coverage is different from the second step coverage.

Abstract: A nanoporous membrane according to the present invention includes a support member and a polymer layer disposed on the support member and including a plurality of nano pores each having an inner wall formed of a block-structured polymer material of which the end thereof is substituted by a functional group.

Abstract: A membrane according to the present invention includes a support member and a polymer layer disposed on the support member and including a plurality of nano pores each having an inner wall formed of a block-structured polymer material of which the end thereof is substituted by a functional group.

Abstract: A membrane according to the present invention includes a support member and a polymer layer disposed on the support member and including a plurality of nano pores each having an inner wall formed of a block-structured polymer material of which the end thereof is substituted by a functional group.