Patents by Inventor Sang-Sik Yoon

Sang-Sik Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120013907
    Abstract: In a cleaning system, dust stored in a dust box is suspended in air introduced into the dust box through a first opening formed through a robot cleaner, and is then discharged to a second opening formed through a maintenance station through the first opening of the robot cleaner.
    Type: Application
    Filed: July 15, 2011
    Publication date: January 19, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun Soo Jung, Dong Won Kim, Jun Hwa Lee, Jun Pyo Hong, Sang Sik Yoon
  • Publication number: 20120011676
    Abstract: In a cleaning system, dust stored in a dust box is suspended in air introduced into the dust box through a first opening formed through a robot cleaner, and is then discharged to a second opening formed through a maintenance station through the first opening of the robot cleaner.
    Type: Application
    Filed: July 15, 2011
    Publication date: January 19, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun Soo JUNG, Dong Won KIM, Jun Hwa LEE, Jun Pyo HONG, Sang Sik YOON
  • Publication number: 20120011677
    Abstract: In a cleaning system, dust stored in a dust box is suspended in air introduced into the dust box through a first opening formed through a robot cleaner, and is then discharged to a second opening formed through a maintenance station through the first opening of the robot cleaner.
    Type: Application
    Filed: July 13, 2011
    Publication date: January 19, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun Soo Jung, Dong Won Kim, Jun Hwa Lee, Jun Pyo Hong, Sang Sik Yoon
  • Patent number: 8065550
    Abstract: A semiconductor memory device includes a mode register set for establishing information on a delay time, a delay time calculator for calculating an I/O path delay time of a data clock on a basis of a unit period of a system clock, and a delay locked clock generator for reflecting in the data clock a value of subtracting an output of the delay time calculator from the information established in the mode register set.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: November 22, 2011
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Bo-Kyeom Kim, Sang-Sik Yoon
  • Patent number: 8031611
    Abstract: A method of generating IP traffic flow based on a time bucket divides, in order to generate flows using all IP packets arriving in a preset time bucket, a previous time bucket flow table (PTBFT) and a current time bucket flow table (CTBFT) with reference to a current time when the flows are generated using IP packets collected from a high-speed line in a flow generating unit. Accordingly, the method allows real-time analysis of flows.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: October 4, 2011
    Assignee: Electronics And Telecommunications Research Institute
    Inventors: Sang Sik Yoon, Sang Wan Kim, Dong Won Kang, Tae Sang Choi, Joon Kyung Lee
  • Patent number: 7983164
    Abstract: An apparatus and method for merging Internet traffic mirrored from multiple links are provided. A merged flow can be generated on the Internet having a characteristic of asymmetrical route through a technology of merging the traffic according to an identical characteristic based on correlation analysis using internet traffic mirrored from several spots of multiple links connected to a network to facilitate general analysis and specific application analysis of traffic.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: July 19, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sang Wan Kim, Sang Sik Yoon, Tae Sang Choi, Dong Won Kang, Joon Kyung Lee
  • Publication number: 20110149746
    Abstract: Provided is a scheme for extracting and detecting a predetermined traffic packet by monitoring a packet stream in a router, more particularly, a method and apparatus of monitoring a packet stream in a router. The apparatus may include a packet stream reading unit to read a packet stream inputted to the router, and an abnormal packet detecting unit to determine whether the read packet stream is abnormal.
    Type: Application
    Filed: December 20, 2010
    Publication date: June 23, 2011
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Dong Won Kang, Joon Kyung Lee, Sang Wan Kim, Sang Kil Park, Sang Sik Yoon
  • Publication number: 20110149727
    Abstract: A traffic control apparatus is provided which includes an interface connector to transmit/receive an Internet Protocol (IP) packet to/from an external circuit, a frame generator to receive the IP packet through the interface connector and to generate a Media Access Control (MAC) frame, and a network processor to transmit/receive the IP packet to/from the frame generator, to execute at least one programmable application, and to identify and classify the at least one programmable application.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 23, 2011
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Sang Sik YOON, Sang Kil Park, Sang Wan Kim, Dong Won Kang, Joon Kyung Lee, Taesang Choi, Kyeong Ho Lee, Young Beom Choi, Ki Dong Nam, Kyung Pyo Jun, Jin Ho Hahm
  • Publication number: 20110149794
    Abstract: Provided are a dynamic flow sampling apparatus and dynamic flow sampling method. According to embodiments of the present invention, by collecting load information about a load of an Internet network and dynamically performing a flow sampling with respect to a packet based on the load information and a reference value, the load on an Internet network device and a data processing time for a traffic analysis may be reduced. Further, since an amount of traffic in a population to be analyzed may increase, reliability on an analysis result may be enhanced.
    Type: Application
    Filed: December 20, 2010
    Publication date: June 23, 2011
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Sang Wan KIM, Sang Sik Yoon, Dong Won Kang, Sang Kil Park, Joon Kyung Lee
  • Publication number: 20110149776
    Abstract: Disclosed are a network interface card device and a traffic processing method using the network interface card device, the method including receiving a packet from a network, determining, by a first chipset, whether a detailed analysis is performed by verifying the received packet, and analyzing in detail, by a second chipset, with respect to a packet using the detailed analysis.
    Type: Application
    Filed: December 20, 2010
    Publication date: June 23, 2011
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Sang Kil PARK, Sang Wan Kim, Sang Sik Yoon, Dong Won Kang, Joon Kyung Lee
  • Patent number: 7848178
    Abstract: Semiconductor memory device and method for operating the same includes a phase detection unit configured to compare a phase of a first reference clock and a phase of a second divided reference clock to output a comparison result signal and a phase control and division unit configured to generate the second divided reference clock by dividing a second reference clock by a predetermined ratio according to the comparison result signal outputted from the phase detection unit and adjusting a phase of the second reference clock.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: December 7, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyung-Hoon Kim, Sang-Sik Yoon
  • Publication number: 20100158007
    Abstract: A method and apparatus for aggregating single packets in a single session are disclosed. If the amount of single packets in a single session exceeds a threshold value, it is detected that attack traffic is being inputted and the single packets in the single session are aggregated into a single flow, thus preventing degradation of a network performance due to the single packets in the single session.
    Type: Application
    Filed: July 22, 2009
    Publication date: June 24, 2010
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Sang Wan Kim, Sang Sik Yoon, Dong Won Kang, Tae Sang Choi, Joon Kyung Lee, You Hyeon Jeong
  • Publication number: 20100135157
    Abstract: There is provided a method and apparatus for controlling traffic according to user that includes a statistics processing unit measuring traffic volume used according to user, calculating a traffic variation ?V by using the measured traffic volume, and updating a traffic user list by comparing the calculated traffic variation ?V; a traffic detecting unit determining whether abnormal traffic is generated in a network and transferring a control command according to priority in the traffic user list; and a packet controlling unit controlling a user's traffic according to the control command received from the traffic detecting unit.
    Type: Application
    Filed: September 15, 2009
    Publication date: June 3, 2010
    Inventors: Sang Wan KIM, Dong Won KANG, Joon Kyung LEE, Sang Sik YOON, Tae Sang CHOI, You Hyeon JEONG
  • Publication number: 20100135182
    Abstract: There is provided a high-speed IP flow mediation apparatus using a network processor. The apparatus includes a server collecting flow information regarding IP traffic on a high-speed line and a network processor board analyzing the collected information according to Internet applications using a network processor, and transferring the analyzed flow information to a plurality of flow analysis systems.
    Type: Application
    Filed: December 2, 2009
    Publication date: June 3, 2010
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Sang Sik YOON, Tae Sang CHOI, Sang Wan KIM, Dong Won KANG, Joon Kyung LEE, Kyeong Ho LEE
  • Patent number: 7730331
    Abstract: Disclosed herein is a method of controlling power consumption of a mobile communication terminal, and a mobile communication terminal in which the method is implemented. The mobile communication terminal, having peripheral devices, such as a speaker, Liquid Crystal Display (LCD) and a camera, and a diversity unit for implementing a diversity function, includes a power measurement unit and a control unit. The power measurement unit measures power consumed in the diversity unit. The control unit controls the power consumption of the peripheral devices based on the amount of consumed power read from the power measurement unit. Accordingly, the power consumption of the peripheral devices is appropriately controlled, so that unnecessary power consumption can be reduced, therefore the lifespan of a battery can be prolonged.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: June 1, 2010
    Assignees: Pantech Co., Ltd., SK Telecom Co., Ltd.
    Inventors: Sang-Sik Yoon, Hong-Woo Lee
  • Publication number: 20090116331
    Abstract: Semiconductor memory device and method for operating the same includes a phase detection unit configured to compare a phase of a first reference clock and a phase of a second divided reference clock to output a comparison result signal and a phase control and division unit configured to generate the second divided reference clock by dividing a second reference clock by a predetermined ratio according to the comparison result signal outputted from the phase detection unit and adjusting a phase of the second reference clock.
    Type: Application
    Filed: December 31, 2007
    Publication date: May 7, 2009
    Inventors: Kyung-Hoon Kim, Sang-Sik Yoon
  • Publication number: 20090119533
    Abstract: A semiconductor memory device includes a mode register set for establishing information on a delay time, a delay time calculator for calculating an I/O path delay time of a data clock on a basis of a unit period of a system clock, and a delay locked clock generator for reflecting in the data clock a value of subtracting an output of the delay time calculator from the information established in the mode register set.
    Type: Application
    Filed: December 28, 2007
    Publication date: May 7, 2009
    Inventors: Bo-Kyeom Kim, Sang-Sik Yoon
  • Publication number: 20090059693
    Abstract: A semiconductor memory device includes: a data multiplexing unit configured to output one of a data training pattern and data transferred through a first global input/output line in response to a training control signal; and a latch unit configured to latch an output of the data multiplexing unit to apply and maintain the latched output to a second global input/output line.
    Type: Application
    Filed: December 28, 2007
    Publication date: March 5, 2009
    Inventors: Ji-Hyae Bae, Sang-Sik Yoon
  • Publication number: 20060242441
    Abstract: Disclosed herein is a method of controlling power consumption of a mobile communication terminal, and a mobile communication terminal in which the method is implemented. The mobile communication terminal, having peripheral devices, such as a speaker, Liquid Crystal Display (LCD) and a camera, and a diversity unit for implementing a diversity function, includes a power measurement unit and a control unit. The power measurement unit measures power consumed in the diversity unit. The control unit controls the power consumption of the peripheral devices based on the amount of consumed power read from the power measurement unit. Accordingly, the power consumption of the peripheral devices is appropriately controlled, so that unnecessary power consumption can be reduced, therefore the lifespan of a battery can be prolonged.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 26, 2006
    Inventors: Sang-Sik Yoon, Hong-Woo Lee
  • Patent number: 6157557
    Abstract: A memory used for both a field configurable RAM and a PLA, comprising a configurable memory block including a CAM block for performing an AND function of the PLA and a RAM block for selectively performing a field configurable RAM function and an OR function of the PLA, each of the CAM and RAM blocks including a plurality of basic memory blocks, each of the basic memory blocks including a plurality of CAM cells, a plurality of interconnection circuits for selectively interconnecting the basic memory blocks, an input controller for controlling a data input operation of the configurable memory block, and an output controller for controlling a data output operation of the configurable memory block. According to the present invention, the length of output data or the number of memory blocks can be adjusted with no loss in area.
    Type: Grant
    Filed: December 29, 1998
    Date of Patent: December 5, 2000
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Kwi-Ro Lee, Sang-Sik Yoon