Abstract: A connector position alignment assembly includes a first part and a second part coupled to each other through a connector and including a guide portion aligning a position of the connector. The guide portion is provided with a guide pin and a guide boss including portions protruding toward each other, and the guide pin and the guide boss respectively protrude further than the connector, in a direction in which the first part and the second part face each other, such that a portion of the guide pin is accommodated in the guide boss before the connectors are coupled to each other.

Abstract: An eco-friendly power source such as a battery module is provided for a transportation vehicle, including: a first sub-module and a second sub-module respectively including a cell stack in which a plurality of battery cells are stacked; and a central wall disposed between the first sub-module and the second sub-module, wherein the central wall includes a first central wall facing the first sub-module and a second central wall facing the second sub-module, wherein the first central wall has a rotationary symmetrical shape of the second central wall around a first axis.

Abstract: An eco-friendly power source, such as a battery module provided for a transportation vehicle includes a first sub-module and a second sub-module disposed in a first direction, the first sub-module and the second sub-module respectively including a plurality of battery cells stacked in a second direction, which is perpendicular to the first direction, and a lower cover coupled to the first sub-module and the second sub-module. The first sub-module and the second sub-module are disposed to be rotationally symmetrical to each other about a central axis, which is perpendicular to both the first direction and the second direction.

Abstract: A battery module is disclosed. In some implementations, the battery module includes: first and second sub-battery modules respectively including a cell stack including a plurality of battery cells and a sensing assembly sensing a state of the plurality of battery cells and an upper cover covering upper portions of the first and second sub-battery modules, wherein the upper cover includes a plurality of through-holes exposing portions of the first and second sub-battery modules, respectively.

Abstract: A battery module includes: first and second sub-battery modules, respectively comprising a cell stack including a plurality of battery cells, and a bus bar assembly disposed at least one side of the cell stack; and a central wall disposed between the first and second sub-battery modules, wherein the central wall includes a hollow venting passage formed in a direction intersecting the direction that the first and second sub-battery modules are disposed such that gas or flames occurring in the first or second sub-battery modules are allowed to flow from inside the battery module through the hollow venting passage to the outside of the battery module.

Abstract: An eco-friendly power source, such as a battery module for a transportation vehicle includes a first sub-module and a second sub-module each including a plurality of battery cells; a lower cover supporting the first sub-module and the second sub-module; a connection member coupled to the first sub-module and the second sub-module, respectively; and a cooling plate coupled to the lower cover and forming a flow path through which a refrigerant can flow, wherein at least a portion of the flow path is disposed to oppose the connection member with the lower cover interposed therebetween.

Abstract: An eco-friendly power source, such as a battery module is provided for a transportation vehicle and includes a plurality of cell assemblies including a first cell assembly and a second cell assembly each including a plurality of battery cells; a connection member connected to the first cell assembly and the second cell assembly, respectively; a lower cover supporting the plurality of cell assemblies; and end cover spaced apart from the connection member, wherein the first cell assembly and the second cell assembly have at least one side opposing the connection member and the other side opposing the end cover.

Abstract: A semiconductor device includes a semiconductor substrate having isolation regions formed therein and a fin-shaped semiconductor structure protruding vertically above the isolation regions and extending laterally in a first direction. The device additionally includes a gate dielectric wrapping a channel region of the fin-shaped semiconductor structure and a gate electrode wrapping the gate dielectric. The channel region is interposed in the first direction between a source region and a drain region and has sloped sidewalls and a width that continuously decreases from a base towards a peak of the channel region. The channel region comprises a volume inversion region having a height greater than about 25% of a total height of the channel region.

Abstract: A semiconductor device includes a semiconductor substrate having isolation regions formed therein and a fin-shaped semiconductor structure protruding vertically above the isolation regions and extending laterally in a first direction. The device additionally includes a gate dielectric wrapping a channel region of the fin-shaped semiconductor structure and a gate electrode wrapping the gate dielectric. The channel region is interposed in the first direction between a source region and a drain region and has sloped sidewalls and a width that continuously decreases from a base towards a peak of the channel region. The channel region comprises a volume inversion region having a height greater than about 25% of a total height of the channel region.

Abstract: A semiconductor device includes a semiconductor substrate having isolation regions formed therein and a fin-shaped semiconductor structure protruding vertically above the isolation regions and extending laterally in a first direction. The device additionally includes a gate dielectric wrapping a channel region of the fin-shaped semiconductor structure and a gate electrode wrapping the gate dielectric. The channel region is interposed in the first direction between a source region and a drain region and has sloped sidewalls and a width that continuously decreases from a base towards a peak of the channel region. The channel region comprises a volume inversion region having a height greater than about 25% of a total height of the channel region.

Abstract: A semiconductor device includes a semiconductor substrate having isolation regions formed therein and a fin-shaped semiconductor structure protruding vertically above the isolation regions and extending laterally in a first direction. The device additionally includes a gate dielectric wrapping a channel region of the fin-shaped semiconductor structure and a gate electrode wrapping the gate dielectric. The channel region is interposed in the first direction between a source region and a drain region and has sloped sidewalls and a width that continuously decreases from a base towards a peak of the channel region. The channel region comprises a volume inversion region having a height greater than about 25% of a total height of the channel region.

Abstract: A semiconductor device includes a semiconductor substrate having isolation regions formed therein and a fin-shaped semiconductor structure protruding vertically above the isolation regions and extending laterally in a first direction. The device additionally includes a gate dielectric wrapping a channel region of the fin-shaped semiconductor structure and a gate electrode wrapping the gate dielectric. The channel region is interposed in the first direction between a source region and a drain region and has sloped sidewalls and a width that continuously decreases from a base towards a peak of the channel region. The channel region comprises a volume inversion region having a height greater than about 25% of a total height of the channel region.

Abstract: A semiconductor device includes a semiconductor substrate having isolation regions formed therein and a fin-shaped semiconductor structure protruding vertically above the isolation regions and extending laterally in a first direction. The device additionally includes a gate dielectric wrapping a channel region of the fin-shaped semiconductor structure and a gate electrode wrapping the gate dielectric. The channel region is interposed in the first direction between a source region and a drain region and has sloped sidewalls and a width that continuously decreases from a base towards a peak of the channel region. The channel region comprises a volume inversion region having a height greater than about 25% of a total height of the channel region.

Abstract: The pressure within a compartment of a refrigerator is kept equalized with ambient atmospheric air to facilitate the opening of the refrigerator door. An air passage capable of communicating the compartment with ambient air is closed when the compartment pressure is equal to the ambient air pressure, and is automatically opened when the compartment pressure become less than the ambient air pressure. The opening of the air passage is under the control of water contained in a trap portion of defrost water drain conduit of the refrigerator. The level of that trapped water fluctuates in height in response to differences in pressure between the compartment and ambient air, and the change in that height is used to open (or close) the air passage. The trapped water itself can be used to block the air passage, or a closure member floating on the water can block the air passage.

Abstract: A novel technique to detect oxydonor generation in semiconductor wafers. Oxydonor generation in a P-type substrate may be sufficient to create a P-N junction within the substrate which may adversely affect device performance. A technique of the present invention is a two-step process for determining the presence of such an oxydonor generated P-N junction. For a capacitor device, the capacitance of the device is measured under varying test voltages to determine a capacitance-voltage response. Then a second capacitance-voltage response is measured when the device is subjected to an external energy source. For a diode device, the forward current is measured with the device under varying test voltages to determine a current-voltage response. Then a second currrent-voltage response is measured when the device is subjected to an external energy source. By comparing device response with and without the application of external energy, a device having oxydonor generation problems is efficiently detected.

Abstract: An error testing process for the testing of CMOS static RAM memories. Individual static RAM memory cells that have failed are isolated. A typical cell has six transistors, two access, two n-channel and two p-channel. The access transistors are allowed to float which effectively isolates the cell. By application of voltages to the n-channel or p-channel transistors one set can be turned off and the remaining two n-channel or p-channel transistors can be tested with microprobes varying voltages for the forward and reverse bias testing. The graphs of the current flow from these tests are compared using the signature analysis technique so that not only the exact transistor which failed can be identified but the failure mechanism can also be identified. This process permits error testing without damage to the RAM memory and without physical isolation of the SRAM memory.

Abstract: This describes four distinct methods of forming copper and silicon doped aluminum conductive structures on the surface of the semiconductor body which when sintered will form in conjunction with the exposed surface of the silicon body Schottky diodes which are resistant to internal field emission characteristics created by co-incidental copper-aluminum precipitates and aluminum doped solid phase epitaxial growths.

Abstract: A method of forming a self aligned guard ring surrounding a schottky barrier diode device without requiring an enlargement of the final schottky barrier device. The method involves creating an overhanging opening in a insulator layer overlying a semiconductor body to expose the schottky contact area on the surface of the semiconductor body, depositing a diffusion barrier material such as molybdenum in the opening, the deposit being of the same size as the smallest part of the overhanging opening so that a guard ring can be formed from a vapor by diffusion around the deposited barrier material.