Abstract: A battery unit for a vehicle is provided. The battery unit includes a lower case having two battery compartments arranged in a direction toward opposite sides of the vehicle, respectively, and a connecting portion bent to be convex upwardly between the two battery compartments. A reinforcing structure is disposed on the connecting portion. Two battery modules are installed in the two battery compartments, respectively and a power wire is electrically connected to at least one of the two battery modules and extends from one of the two battery compartments to the other one of the two battery compartments through the connecting portion.

Abstract: A semiconductor memory device includes: a first gate stack structure including first interlayer insulating layers and first conductive layers, which are alternately stacked in a vertical direction; a dummy vertical channel penetrating the first gate stack structure; lower vertical channels penetrating the first gate stack structure at both sides of the dummy vertical channel; a second gate stack structure including second interlayer insulating layers and second conductive layers, which are alternately stacked in the vertical direction on the first gate stack structure; a first select line isolation structure partially penetrating the second gate stack structure; upper vertical channels connected to the lower vertical channels while penetrating the second gate stack structure; and a second select line isolation structure overlapping with the dummy vertical channel in the vertical direction, the second select line isolation structure penetrating a portion of the second gate stack structure.

Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure including a plurality of conductive patterns and a plurality of interlayer insulating layers, which are alternately stacked on a substrate; a plurality of channel structures extending in a first direction substantially perpendicular to the substrate to penetrate the stack structure; at least one first slit extending in a second direction substantially horizontal to the substrate while penetrating conductive patterns for select lines among the plurality of conductive patterns; a second slit extending in the second direction while penetrating the conductive patterns for select lines; and a plurality of support structures disposed on a bottom of the second slit, the plurality of support structures penetrating conductive patterns for word lines among the plurality of conductive patterns.

Abstract: A semiconductor memory device, and a method of manufacturing the same, includes a lower stack in which a plurality of first interlayer insulating layers and first conductive layers are alternately stacked, a plurality of cell plugs passing through the lower stack in a vertical direction, an upper stack in which a plurality of second interlayer insulating layers and at least one second conductive layer are alternately stacked on the lower stack, a plurality of drain select plugs passing through the upper stack and being in contact with an upper portion of the plurality of cell plugs, and a separation pattern separating adjacent drain select plugs among the plurality of drain select plugs, wherein the separation pattern is in contact with a sidewall of each of the adjacent drain select plugs.

Abstract: The present invention relates to methods for forming one or more thin film layers on a substrate, to form a multilayer product such as a lithium battery cell. The method involves passing a gas stream comprising at least one doping agent and at least one entrained source material through a plasma; impinging the gas stream on a substrate; and reactively depositing the at least one doping agent, and the at least one entrained source material on the substrate. The present invention provides a method of fabricating a power cell having a plurality of layers, and a method of fabricating a battery by electrically connecting a current collecting layer of a first power cell to a current collecting layer of a second power cell.

Abstract: A thin film transistor array panel includes an insulating substrate, a gate line disposed on the insulating substrate having a gate electrode, a first gate insulating layer disposed on the gate line and made of silicon nitride, a second gate insulating layer disposed on the first gate insulating layer and made of silicon oxide, an oxide semiconductor disposed on the second gate insulating layer, a data line disposed on the oxide semiconductor and having a source electrode, a drain electrode disposed on the oxide semiconductor and facing the source electrode, and a pixel electrode that is connected to the drain electrode. A thickness of the second gate insulating layer may range from 200 ? to less than 500 ?.

Abstract: A thin-film transistor (TFT) includes a gate electrode, an oxide semiconductor pattern, a source electrode, a drain electrode and an etch stopper. The gate electrode is formed on a substrate. The oxide semiconductor pattern is disposed in an area overlapping with the gate electrode. The source electrode is partially disposed on the oxide semiconductor pattern. The drain electrode is spaced apart from the source electrode, faces the source electrode, and is partially disposed on the oxide semiconductor pattern. The etch stopper has first and second end portions. The first end portion is disposed between the oxide semiconductor pattern and the source electrode, and the second end portion is disposed between the oxide semiconductor pattern and the drain electrode. A sum of first and second overlapping length is between about 30% and about 99% of a total length of the etch stopper.

Abstract: The present invention relates to methods for forming one or more thin film layers on a substrate, to form a multilayer product such as a lithium battery cell. The method involves passing a gas stream comprising at least one doping agent and at least one entrained source material through a plasma; impinging the gas stream on a substrate; and reactively depositing the at least one doping agent, and the at least one entrained source material on the substrate. The present invention provides a method of fabricating a power cell having a plurality of layers, and a method of fabricating a battery by electrically connecting a current collecting layer of a first power cell to a current collecting layer of a second power cell.