Abstract: A light module includes a first light emitter, a second light emitter, a third light emitter, and a controller. The first light emitter is configured to emit a first light having a first peak wavelength in a visible range, the second light emitter is configured to emit a second light having a waveform having a second peak wavelength higher than the first peak wavelength, and the third light emitter is configured to emit a third light having a third peak wavelength that is shorter than the first peak wavelength. The controller is configured to control the first light emitter, the second light emitter, and the third light emitter to generate a first light pattern and a second light pattern. The first light pattern comprises a first light spectrum and the second light pattern comprises a second light spectrum including at least one more peak wavelength than the first light spectrum.

Abstract: An apparatus for predicting a traffic speed and a method thereof are provided. The apparatus includes an input device that receives traffic speed sequences of a plurality of links and a controller that detects a spatio-temporal relationship between traffic speeds of the plurality of links and predicts a future traffic speed of a target link based on the spatio-temporal relationship between the traffic speeds of the plurality of links.

Abstract: Provided is a reflector/scatterer arranged around a side lobe beam which is generated from a transmission antenna, in a radiation direction of the side lobe beam, for use in expanding a communication service coverage area.

Abstract: An inductor includes a first magnetic body having a toroidal shape and having a ferrite; and a second magnetic body configured to be different from the first magnetic body and including a metal ribbon, wherein the second magnetic body includes an outer magnetic body disposed on an outer circumferential surface of the first magnetic body and an inner magnetic body disposed on an inner circumferential surface of the first magnetic body, and each of the outer magnetic body and inner magnetic body is wound in a plurality of layers in a circumferential direction of the first magnetic body.

Abstract: The present disclosure relates to a positive active material for a lithium rechargeable battery, a manufacturing method thereof, and a lithium rechargeable battery including the positive active material, and it provides a positive active material which is a lithium composite metal oxide including nickel, cobalt, and manganese, and either has orientation in a direction of with respect to an ND axis that is equal to or greater than 29% or has orientation in a direction of [120]+[210] with respect to an RD axis that is equal to or greater than 82% in the case of an EBSD analysis with a misorientation angle (?g) that is equal to or less than 30 degrees.

Abstract: A light source includes a controller configured to turn on or off a plurality of light sources depending on a light period. The controller can be configured to turn on the light sources during each of a plurality of light periods such that the light sources emit a light having a spectrum with a plurality of peaks toward the plant. At least one light period can include a first period and a second period and the first period preceding or following the second period. The controller can adjust the spectrum of the light between the first period and the second period and/or during different light periods.

Abstract: A system comprising a first double data rate (DDR) memory device, a second DDR memory device coupled to the first DDR memory device, the second DDR memory device not using a delay locked loop (DLL) device to synchronize clock signals. The system further comprises a logic coupled to the first and second DDR memory devices. The logic is adapted to receive data from the first and second DDR memory devices by way of a single conductive pathway.

Abstract: An electronic circuit including a power managed circuit (2610), and a power management control circuit (3570) coupled to the power managed circuit (2610) and operable to select between at least a first operating performance point (OPP1) and a second higher operating performance point (OPP2) for the power managed circuit (2610), each performance point including a respective pair (Vn, Fn) of voltage and operating frequency, and the power management control circuit (3570) further operable to control dynamic power switching of the power managed circuit (2610) based on a condition wherein the power managed circuit (2610) at a given operating performance point has a static power dissipation (4820.1), and the dynamic power switching puts the power managed circuit in a lower static power state (4860.1) that dissipates less power than the static power dissipation (4820.1).

Abstract: A system comprising a first double data rate (DDR) memory device, a second DDR memory device coupled to the first DDR memory device, the second DDR memory device not using a delay locked loop (DLL) device to synchronize clock signals. The system further comprises a logic coupled to the first and second DDR memory devices. The logic is adapted to receive data from the first and second DDR memory devices by way of a single conductive pathway.

Abstract: A system comprises a display controller adapted to monitor a first-in, first-out module (“FIFO”) data level, a memory controller coupled to said display controller, and a memory coupled to said display controller and said memory controller. The memory controller permits the display controller to immediately access the memory when the FIFO data level drops below a pre-determined threshold level and no display panel horizontal or vertical blanking periods are in progress.

Abstract: A method, comprising determining parameters for a first window and a second window on a display screen, said first window superimposed in front of the second window. The method further comprises determining which areas of the second window are not superimposed by the first window and dividing the areas into multiple portions, each portion abutting a separate side of the first window. For each of the portions, the method comprises fetching pixel data from a memory using an addressing mode suitable for said portion and displaying said pixel data on the display screen.

Abstract: A data processing device uses a portion of random access memory 121 as an output buffer 124 for holding a portion of a stream of PCM data which is to be output to a digital to analog converter 530. D/A 530 forms a left analog channel and a right analog channel for speaker subsystems 814 and 815. The PCM data stream is stored in the output buffer so that PCM data samples which pertain to the left channel are stored at even address and PCM data samples which pertain to the right channel are stored at odd address. Control circuitry 145 monitors direct memory access (DMA) transfers which transfer PCM data samples to PCM serializer 142. By comparing the address of each DMA transfer to a left/right channel signal from the D/A, the control circuitry can verify that channel synchronization is correct. If a synchronization error is detected, an channel synchronization error correction procedure is invoked.

Abstract: An adder includes carry generation & propagation circuits, a carry evaluation circuit and a final sum circuit, wherein the carry generation & propagation circuit and the sum circuit are composed of transmission gates, and the operation can be carried out having a reduced number of stages, thereby decreasing layout area and increasing speed.