Abstract: A display system comprises a mapping memory comprising a plurality of memory banks configured to store a plurality of image tiles corresponding to an image, and an image mapping component configured to assign each of the plurality of tiles to one of the plurality of memory banks according to a first mapping or a second mapping, wherein the image mapping component determines whether to use the first or second mapping based on a bank interleaving metric of the first and second mappings.

Abstract: A display system comprises a mapping memory comprising a plurality of memory banks configured to store a plurality of image tiles corresponding to an image, and an image mapping component configured to assign each of the plurality of tiles to one of the plurality of memory banks according to a first mapping or a second mapping, wherein the image mapping component determines whether to use the first or second mapping based on a bank interleaving metric of the first and second mappings.

Abstract: A method of modulating data, which is represented by two data types of ‘high’ and ‘low’, and demodulating the modulated data, is disclosed. In a method of data modulation and demodulation for a communication system which has a transmitting end modulating a data and a receiving end demodulating the transmitted data from the transmitting end, the data is represented by two types including ‘high’ and ‘low’, and the receiving end receives at least one data which consists of at least one code-word spread by a unique orthogonal code. The receiving end adds up the received data in the unit of code-word, and subtracts the length of the orthogonal code from a value which is obtained by doubling the sum of the code-word, when the code-word of the orthogonal code is ‘0’. The receiving end then averages the result after the subtraction in the unit of orthogonal code length and extracts the result, and therefore, obtains the data from the transmitting end.

Abstract: A display system comprises a mapping memory comprising a plurality of memory banks configured to store a plurality of image tiles corresponding to an image, and an image mapping component configured to assign each of the plurality of tiles to one of the plurality of memory banks according to a first mapping or a second mapping, wherein the image mapping component determines whether to use the first or second mapping based on a bank interleaving metric of the first and second mappings.

Abstract: A display system comprises a mapping memory comprising a plurality of memory banks configured to store a plurality of image tiles corresponding to an image, and an image mapping component configured to assign each of the plurality of tiles to one of the plurality of memory banks according to a first mapping or a second mapping, wherein the image mapping component determines whether to use the first or second mapping based on a bank interleaving metric of the first and second mappings.

Abstract: A method of modulating data, which is represented by two data types of ‘high’ and ‘low’, and demodulating the modulated data, is disclosed. In a method of data modulation and demodulation for a communication system which has a transmitting end modulating a data and a receiving end demodulating the transmitted data from the transmitting end, the data is represented by two types including ‘high’ and ‘low’, and the receiving end receives at least one data which consists of at least one code-word spread by a unique orthogonal code. The receiving end adds up the received data in the unit of code-word, and subtracts the length of the orthogonal code from a value which is obtained by doubling the sum of the code-word, when the code-word of the orthogonal code is ‘0’. The receiving end then averages the result after the subtraction in the unit of orthogonal code length and extracts the result, and therefore, obtains the data from the transmitting end.

Abstract: A packet data communication on-chip interconnect system is provided including a network interface efficiently controlling a transaction performed between at least one master intellectual property (IP) block and at least one slave IP block connected via a Network on a Chip (NoC). According to an aspect of the present invention, traffic functioning and throughput of the entire NoC may be improved by appropriately controlling an operation of performing a lock operation according to an Advance eXtensible Interface (AXI) protocol in the network interface of the packet data communication on-chip interconnect system.

Abstract: A switching device of NoC (Networks on Chip) system and a scheduling method thereof. The switching device has a switching part having a plurality of input ports and a plurality of output ports, and a scheduler for setting a transmission route between the input ports and the output ports, determining the length of code based on the number of input ports having the data among the plurality of input ports, and assigning a predetermined code of the determined code length to the input port and the output port corresponding to the set transmission route. Because the code length is adjustably varied according to the number of transmission packets, switch performance improves.

Abstract: An apparatus and a method for setting a routing path in System-on-a-Chip (SoC) having an n×n net topology-based structure comprising a plurality of intellectual properties (IPs), each with a unique address, and a plurality of switches forming one-to-one correspondence to the IPs, to transmit and receive data between the IPs by using at least one of the switches. Accordingly, an orthogonal code having orthogonality is assigned according to the direction of transmission of each data (that is, output port). Then, an output port where the data is transmitted is determined, and the data is spread based on an orthogonal code assigned to the output ports of the at least one of the switches.

Abstract: An apparatus and a method for setting a routing path in System-on-a-Chip (SoC) having an n×n net topology-based structure comprising a plurality of intellectual properties (IPs), each with a unique address, and a plurality of switches forming one-to-one correspondence to the IPs, to transmit and receive data between the IPs by using at least one of the switches. Accordingly, an orthogonal code having orthogonality is assigned according to the direction of transmission of each data (that is, output port). Then, an output port where the data is transmitted is determined, and the data is spread based on an orthogonal code assigned to the output ports of the at least one of the switches.

Abstract: A method of establishing a path between routers in a system-on-chip (SoC) of n×n mesh topology structure having a plurality of intellectual properties (IPs) each with a unique address and routers corresponding to each of the IPs respectively, including: receiving a routing packet including a hop counter, and updating address information and information of a stored routing table; establishing a path to at least one neighboring router using the updated routing table upon a request to establish the path; and delivering data by using the established path.

Abstract: A network on chip (NoC) response signal control apparatus and an NoC response signal control method using the apparatus are provided. The NoC response signal control apparatus includes: a network interface (NI) slave which outputs an enabling signal for a response signal via a response signal wire if a predetermined response signal is input from a slave intellectual property (IP); and an NI master which outputs a transaction to a master IP by generating the transaction for the response signal if the enabling signal is input via the response signal wire which is directly connected to the NI slave.

Abstract: An urgent packet latency control of a network on chip (NoC) apparatus and a method of urgent packet latency control of a NoC are provided. The urgent NoC packet latency control apparatus includes: an urgent packet determination unit which determines whether a packet is an urgent packet based on a predetermined field of the packet; an urgent packet path search unit which searches for at least one router, included in a routing path of the urgent packet, if the urgent packet determination unit determines that the packet is urgent; and an urgent packet path control unit which transmits output port information of the urgent packet to the router.

Abstract: Provided are an apparatus for and a method of controlling electric power of a network-on-chip (NoC). The apparatus for controlling electric power of a network-on-chip (NoC), including: a transaction monitoring unit which monitors a transaction generated from at least one of a master and a module corresponding to the master; and a clock control unit which selectively controls clock signal with respect to modules comprising the NoC, based on the monitored transaction.

Abstract: A GALS-based network-on-chip (NoC) includes a plurality of asynchronous first-in first-out (FIFO) input buffers connected to a plurality of IPs that asynchronously receive data; a plurality of asynchronous FIFO output buffers connected to the plurality of IPs asynchronously output data; and a router for forwarding data input to the plurality of asynchronous FIFO input buffers, to an asynchronous FIFO output buffer, among the plurality of asynchronous FIFO output buffers, which is connected to an IP to which the data is destined. Accordingly, the system-on-chip (SoC) adopting the GALS design scheme can transfer data via the NoC between the IPs which are in time zones having different clocks in the centralized switching system, thereby avoiding the need for a point-to-point system.

Abstract: A bus inverting code generating apparatus and a method of generating bus inverting code is provided. The bus inverting code generating apparatus includes a bit comparator comparing present input data with previous input data for each bit and outputs a bit comparison result; a bit counter counting bits of the bit comparison result and outputs a bit count result; an indicator toggling an indicator output if the bit count result that is output by the bit counter is greater than a reference value; and an inverting determiner outputting an inverting signal indicating whether the present input data is inverted based on the bit count result and the indicator output.

Abstract: An input buffer device and control method of the input buffer device. The input buffer device includes a virtual output queuing (VOQ) buffering section which has a plurality of VOQ buffers. The input buffer device stores data which is input to an input port to a VOQ buffer corresponding to an intended output port of the data among the plurality of VOQ buffers. A shared buffering section is provided which stores the data when a VOQ buffer corresponding to the intended output port of the data is full of data. The stored data is forwarded to the VOQ buffer when the VOQ buffer is empty. Accordingly, the input buffer device can more efficiently process the data by use of the fixed-length FIFO buffers and the shared buffer.

Abstract: A computer chip including a plurality of routers, each of the plurality of the routers connected to the adjacent routers in the directions of an X axis and a Y axis; and a plurality of intellectual properties, each of the plurality of the intellectual properties connected to only one of the plurality of the routers.

Abstract: A network on chip system employing an advanced extensible interface protocol is provided. The network on chip system employing the advanced extensible interface protocol includes a plurality of intellectual properties (IPs) which are installed in a chip and read and write data; a router which is connected to the plurality of IPs and transmits data; and a plurality of network interfaces (NIs), each NI corresponding to a respective one of the plurality of IPs and installed between the respective IP and the router, wherein each NI is configured to process data transmitted between the respective IP and the router and to divide data provided from the respective IP into at least one packet.

Abstract: A Network-on-Chip (NoC) system employing an Advanced extensible Interface (AXI) protocol is provided. The NoC includes an NoC router which classifies data transmitted from a plurality of AXI Intellectual Properties (IPs) according to a destination AXI IP, and a network interface (NI) which processes data from the NoC router and provides the processed data to the destination IP. One of the NoC router and the NI includes a plurality of buffers which store data provided from each of the AXI IPs and classified according to each of the AXI IPs, and an interleaving manager which selects buffers, from which data is retrieved, among the plurality of buffers according to an interleaving acceptance capability which is a number of interleaving data that can be accepted by the destination AXI IP.