Abstract: A tire pressure monitoring device of an electric vehicle includes a wheel speed sensor sensing a speed of each wheel of the electric vehicle, and a controller selectively calculating an intercept value of ?FR and a cumulative average value of the ?FR based on a difference between a torque of a front wheel motor and a torque of a rear wheel motor, calculating an intercept value of ?LR and an intercept value of ?Diag based on the speed of each wheel, and monitoring a tire pressure of each wheel based on the calculated intercept value of the ?FR or the cumulative average value of the ?FR, the calculated intercept value of the ?LR, and the calculated intercept value of the ?Diag.

Abstract: An inverted nanocone structure of the present disclosure includes a first surface, a second surface spaced apart from the first surface by a predetermined distance and having a greater area than the first surface, and a body having an inverted cone shape between the first surface and the second surface, wherein at least one activated point defect center is provided in the body.

Abstract: An LED lighting apparatus capable of color temperature control includes a color temperature controller to receive a color temperature selection signal and output first and second control signals; a LED driver connected a plurality of LED groups; and a LED selection circuit including a first switch connected to a first node to which a rectified voltage is applied and receiving the first control signal, a first LED group selectively connected to the first node by the first switch, a second LED group connected in scales with the first LED group, a third LED group selectively connected to the first node by the first switch, a fourth LED group connected in series with the third LED group, and a second switch for selectively connecting the output terminal of the second LED group or the fourth LED group to the LED driver by receiving the second control signal.

Abstract: A digital processing system including a master chip having a first clock pin and a first data pin and a first slave chip having a second clock pin and a second data pin may be provided. The digital processing system may transmit first data from the master chip to the first slave chip based on a synchronous scheme in which a first clock signal output from the master chip via the first clock pin and the first data output from the master chip via the first data pin are provided together and the first data is transmitted in synchronization with the first clock signal, and may transmit second data from the first slave chip to the master chip based on an asynchronous scheme in which the second data output from the first slave chip via the second data pin is transmitted regardless of the first clock signal.

Abstract: Provided is clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator includes a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate a delay clock signal, and output the delay clock signal, a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value, and a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.

Abstract: A digital processing system including a master chip having a first clock pin and a first data pin and a first slave chip having a second clock pin and a second data pin may be provided. The digital processing system may transmit first data from the master chip to the first slave chip based on a synchronous scheme in which a first clock signal output from the master chip via the first clock pin and the first data output from the master chip via the first data pin are provided together and the first data is transmitted in synchronization with the first clock signal, and may transmit second data from the first slave chip to the master chip based on an asynchronous scheme in which the second data output from the first slave chip via the second data pin is transmitted regardless of the first clock signal.

Abstract: The present invention provides a random number generation system comprising: an image sensor module for outputting dark noise generated from each unit pixel region respectively that is shielded from external light as digital data; and a control unit for classifying the respective pieces of digital data output from the image sensor module, for allocating random numbers to the same using a database in which a plurality of reference values are stored for each unit pixel, and for collating the same so as to generate a first random number.

Abstract: The present disclosure relates to a method of manufacturing a sulfide solid electrolyte and a sulfide solid electrolyte manufactured thereby, and more particularly to a method of manufacturing a sulfide solid electrolyte and a sulfide solid electrolyte manufactured thereby, in which the sulfide solid electrolyte includes two or more sulfide compounds, thus improving the atmospheric stability of the solid electrolyte and reducing the generation of toxic gas.

Abstract: In an operating method of a radio frequency integrated circuit (RFIC) including a transmission circuit and a reception circuit, the operating method includes receiving, from a modem, first information for setting transmission power of the transmission circuit or second information about a blocker which is a frequency signal unused by the RFIC, obtaining an allowable value of phase noise of a local oscillator included in the transmission circuit, using the first information, obtaining an allowable value of phase noise of a local oscillator included in the reception circuit, using the second information, determining a level of a driving voltage, using the obtained allowable values of the phase noises, and providing the driving voltage to the local oscillators.

Abstract: A crystal oscillator including a feedback circuit, and a reference clock generating circuit including the crystal oscillator. The crystal oscillator is configured to generate an oscillating signal based on a natural frequency of a crystal. The crystal oscillator may include: a current generating circuit connected to a first node having a first voltage and a second node having a second voltage, and configured to output a first current to the second node; a feedback circuit connected to the generating circuit via the first and second nodes and configured to adjust a level of the second voltage by controlling a level of the first voltage; and a crystal circuit connected to the second node and configured to generate the oscillating signal based on the second voltage.

Abstract: An LED lighting apparatus capable of color temperature control includes a color temperature controller to receive a color temperature selection signal and output first and second control signals; a LED driver connected a plurality of LED groups; and a LED selection circuit including a first switch connected to a first node to which a rectified voltage is applied and receiving the first control signal, a first LED group selectively connected to the first node by the first switch, a second LED group connected in scales with the first LED group, a third LED group selectively connected to the first node by the first switch, a fourth LED group connected in series with the third LED group, and a second switch for selectively connecting the output terminal of the second LED group or the fourth LED group to the LED driver by receiving the second control signal.

Abstract: An LED lighting apparatus capable of color temperature control includes a color temperature controller to receive a color temperature selection signal and output first and second control signals; a LED driver connected a plurality of LED groups; and a LED selection circuit including a first switch connected to a first node to which a rectified voltage is applied and receiving the first control signal, a first LED group selectively connected to the first node by the first switch, a second LED group connected in series with the first LED group, a third LED group selectively connected to the first node by the first switch, a fourth LED group connected in series with the third LED group, and a second switch for selectively connecting the output terminal of the second LED group or the fourth LED group to the LED driver by receiving the second control signal.

Abstract: This specification discloses a quantum public-key cryptosystem. The quantum public-key cryptosystem may use two rotation operators R{circumflex over (n)}(?) and R{circumflex over (m)}(?) satisfying a cyclic evolution. The two rotation operators R{circumflex over (n)}(?) and R{circumflex over (m)}(?) do not have a commutation relation or an anti-commutation relation with each other. The commutation relation or the anti-commutation relation is established when either of the following conditions is satisfied: ?=2i?, ?=2j?, or {circumflex over (n)}·{circumflex over (m)}=1 (i, j=integer), and ?=(2k+1)?, ?=(2l+1)?, or {circumflex over (n)}·{circumflex over (m)}=0 (k, l=integer).

Abstract: A lighting apparatus including an LED circuit including a plurality of serially connected stages configured to receive a modulated rectified voltage, each of the stages including a first path including a first resistor and a first LED connected in series, and a second path connected to the first path in parallel and including a second LED configured to emit light having a color temperature different from that emitted from the first LED, and a driving current controller configured to adjust an intensity of light output from the LED circuit by adjusting currents applied to driving nodes connected to the stages, depending on a dimming signal associated with a dimming level of the rectified voltage, in which a threshold voltage of the first LED is lower than that of the second LED.

Abstract: Provided is clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator includes a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate a delay clock signal, and output the delay clock signal, a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value, and a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.

Abstract: Provided is clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator includes a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate a delay clock signal, and output the delay clock signal, a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value, and a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.

Abstract: In an operating method of a radio frequency integrated circuit (RFIC) including a transmission circuit and a reception circuit, the operating method includes receiving, from a modem, first information for setting transmission power of the transmission circuit or second information about a blocker which is a frequency signal unused by the RFIC, obtaining an allowable value of phase noise of a local oscillator included in the transmission circuit, using the first information, obtaining an allowable value of phase noise of a local oscillator included in the reception circuit, using the second information, determining a level of a driving voltage, using the obtained allowable values of the phase noises, and providing the driving voltage to the local oscillators.

Abstract: A crystal oscillator including a feedback circuit, and a reference clock generating circuit including the crystal oscillator. The crystal oscillator is configured to generate an oscillating signal based on a natural frequency of a crystal. The crystal oscillator may include: a current generating circuit connected to a first node having a first voltage and a second node having a second voltage, and configured to output a first current to the second node; a feedback circuit connected to the generating circuit via the first and second nodes and configured to adjust a level of the second voltage by controlling a level of the first voltage; and a crystal circuit connected to the second node and configured to generate the oscillating signal based on the second voltage.

Abstract: The present invention relates to a nickel-based catalyst for oxidizing carbon monoxide, which is prepared by forming nickel oxide on the surface of a mesoporous support by one or more cycles of atomic layer deposition, and a use thereof. The nickel-based catalyst for oxidizing carbon monoxide according to the present invention is stable at high temperatures because the size of the nickel oxide particles can be restricted to nanometer scales even at high-temperature conditions. In addition, the nickel-based catalyst exhibits catalytic reactivity for oxidation of carbon monoxide even at room temperatures. Additionally, the catalytic activity, which has been deactivated after conducting the catalytic reaction, can be regenerated through annealing and increased gradually through repeated annealing.

Abstract: Provided is clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator includes a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate a delay clock signal, and output the delay clock signal, a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value, and a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.