Abstract: An apparatus and method for allocating a channel using an auction algorithm in a wireless communication system. The method includes measuring a data rate of each channel; selecting one of the channels, when information on the channels is received from a base station, using the received information on the channels and the measured data rate; and determining a bidding price of the selected channel. Performance of the entire system can be improved by reducing complexity as well as guaranteeing an optimal value in the channel allocation.

Abstract: In accordance with an embodiment of the present invention, control device and method are disclosed for reducing unnecessary data backup and restoring operations and increasing data read and write speed in a flash memory. The method includes writing data received from the host system to the flash memory; moving valid data in the basic block to the first link block when a use ratio of the first link block is greater than a reference value; and moving valid data in the first link block to the second link block when a use ratio of the first link block is less than the reference value.

Abstract: The present invention provides a CMOS image sensor for broadening a dynamic range by controlling an integration time for each pixel to thereby obtain a high quality image with a low noise. The CMOS image sensor according to the present invention includes plural pixels, each for storing an integration time of a present frame, and control means for controlling the integration time of a next frame based on the stored integration time.

Abstract: In accordance with an embodiment of the present invention, control device and method are disclosed for reducing unnecessary data backup and restoring operations and increasing data read and write speed in a flash memory. The method includes writing data received from the host system to the flash memory; moving valid data in the basic block to the first link block when a use ratio of the first link block is greater than a reference value; and moving valid data in the first link block to the second link block when a use ratio of the first link block is less than the reference value.

Abstract: The method and device for accessing a flash memory array receives a logical address for the flash memory array, which has been divided into a plurality of blocks. Each block of the flash memory array includes logical address to physical address conversion information for that block. After determining which block the received logical address corresponds, the conversion information for that block is obtained and stored. Memory access operations are then performed using the stored conversion information.

Abstract: The method and device for accessing a flash memory array receives a logical address for the flash memory array, which has been divided into a plurality of blocks. Each block of the flash memory array includes logical address to physical address conversion information for that block. After determining which block the received logical address corresponds, the conversion information for that block is obtained and stored. Memory access operations are then performed using the stored conversion information.

Abstract: A wear leveling system and method of a flash memory cell uses the amount of time required to perform an erasing operation on a sector of the flash memory to determine whether the memory cells in the sector have degraded to an unacceptable level. The actual time required to erase a sector of a flash memory array is compared to a reference erasing time required to erase a unit sector under the state of the worst allowable degradation. If the actual erasing time of a sector exceeds the reference erasing time, logical addresses corresponding to the sector are re-mapped to the physical addresses of a different sector. On the other hand, when the actual erasing time is shorter than or equal to the reference erasing time, a controller continues to use the unit sector.