Patents by Inventor Sang Yee Loong
Sang Yee Loong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7781895Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.Type: GrantFiled: June 17, 2009Date of Patent: August 24, 2010Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Bei Chao Zhang, Chun Hui Low, Hong Lim Lee, Sang Yee Loong, Qiang Guo
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Patent number: 7691739Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.Type: GrantFiled: March 13, 2006Date of Patent: April 6, 2010Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Bei Chao Zhang, Chun Hui Low, Hong Lim Lee, Sang Yee Loong, Qiang Guo
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Publication number: 20090250818Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.Type: ApplicationFiled: June 17, 2009Publication date: October 8, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Bei Chao Zhang, Chun Hui Low, Hong Lim Lee, Sang Yee Loong, Qiang Guo
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Patent number: 7045455Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.Type: GrantFiled: October 23, 2003Date of Patent: May 16, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Beichao Zhang, Chun Hui Low, Hong Lim Lee, Sang Yee Loong, Qiang Guo
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Patent number: 6963113Abstract: A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions.Type: GrantFiled: August 10, 2004Date of Patent: November 8, 2005Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Ting Cheong Ang, Sang Yee Loong, Shyue Fong Quek, Jun Song
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Patent number: 6787422Abstract: A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions.Type: GrantFiled: January 8, 2001Date of Patent: September 7, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Ting Cheong Ang, Sang Yee Loong, Shyue Fong Quek, Jun Song
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Patent number: 6764914Abstract: A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures.Type: GrantFiled: November 7, 2002Date of Patent: July 20, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Alex See, Cher Liang Randall Cha, Shyue Fong Quek, Ting Cheong Ang, Wye Boon Loh, Sang Yee Loong, Jun Song, Chua Chee Tee
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Patent number: 6737739Abstract: A semiconductor chip device package comprised of a semiconductor substrate having semiconductor devices formed on the semiconductor substrate. At least one dielectric layer is over the semiconductor substrate. At least one layer of interconnects is over the semiconductor devices and within the at least one respective dielectric layer with at least a portion of the interconnects being separated by voids having a vacuum or air therein. A passivation layer is over the uppermost of the at least one layer of interconnects. Wherein the semiconductor chip device is vacuum sealed within a semiconductor chip device package.Type: GrantFiled: October 30, 2002Date of Patent: May 18, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Shyue-Fong Quek, Ting Cheong Ang, Duay Ing Ong, Sang Yee Loong
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Patent number: 6653674Abstract: A semiconductor device is provided having angled dopant implantation and vertical trenches in the silicon on insulator substrate adjacent to the sides of a semiconductor gate. A second dopant implantation is in the exposed the source/drain junctions. Contacts having inwardly curved cross-sectional widths in the semiconductor substrate connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.Type: GrantFiled: August 23, 2002Date of Patent: November 25, 2003Assignee: Chartered Semiconductor Manufacturing LTDInventors: Shyue Fong Quek, Ting Cheong Ang, Sang Yee Loong, Puay Ing Ong
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Patent number: 6611024Abstract: An integrated microelectronics semiconductor circuit fabricated on a silicon-on-insulator (SOI) type substrate can be protected from unwanted current surges and excessive heat buildup during fabrication by means of a heat-dissipating, protective plasma-induced-damage (PID) diode. The present invention fabricates such a protective diode as a part of the overall scheme in which the transistor devices are formed.Type: GrantFiled: September 6, 2001Date of Patent: August 26, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Ting Cheong Ang, Shyue Fong Quek, Sang Yee Loong, Jun Song
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Patent number: 6582856Abstract: A new method of fabricating a rim phase shifting mask is achieved. An opaque layer is provided overlying a transparent substrate. A resist layer is deposited overlying the opaque layer. The resist layer is patterned. The opaque layer and the transparent substrate are etched. The resist layer masks this etching. The opaque layer is etched through during this etching. Notches are thereby etched into the transparent substrate at the edges of the opaque layer. These notches will cause a phase shift in incident light relative to incident light passing through regions in the transparent substrate adjacent to the notches. During this etching, an overetch is performed to remove any mask defects in the transparent substrate. Optionally, the notches may be etched into a phase shifting layer overlying the transparent substrate. An etch stopping layer may also be used in the phase shifting layer embodiment.Type: GrantFiled: February 28, 2000Date of Patent: June 24, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Shyue Fong Quek, Ting Cheong Ang, Jun Song, Sang Yee Loong
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Publication number: 20030104673Abstract: A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures.Type: ApplicationFiled: November 7, 2002Publication date: June 5, 2003Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Alex See, Cher Liang Randall Cha, Shyue Fong Quek, Ting Cheong Ang, Wye Boon Loh, Sang Yee Loong, Jun Song, Chua Chee Tee
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Publication number: 20030052403Abstract: A semiconductor chip device package comprised of a semiconductor substrate having semiconductor devices formed on the semiconductor substrate. At least one dielectric layer is over the semiconductor substrate. At least one layer of interconnects is over the semiconductor devices and within the at least one respective dielectric layer with at least a portion of the interconnects being separated by voids having a vacuum or air therein. A passivation layer is over the uppermost of the at least one layer of interconnects. Wherein the semiconductor chip device is vacuum sealed within a semiconductor chip device package.Type: ApplicationFiled: October 30, 2002Publication date: March 20, 2003Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Shyue-Fong Quek, Ting Cheong Ang, Duay Ing Ong, Sang Yee Loong
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Patent number: 6530380Abstract: A method for completely removing dielectric layers formed selectively upon a substrate employed within a microelectronics fabrication from regions wherein closely spaced structures such as self-aligned metal silicide (or salicide) electrical contacts may be fabricated, with improved properties and with attenuated degradation. There is first provided a substrate with employed within a microelectronics fabrication having formed thereon patterned microelectronics layers with closely spaced features. There is then formed a salicide block layer employing silicon oxide dielectric material which may be selectively doped. There is then formed over the substrate a patterned photoresist etch mask layer. There is then etched the pattern of the patterned photoresist etch mask layer employing dry plasma reactive ion etching. An anhydrous etching environment is then employed to completely remove the silicon oxide dielectric salicide block layer with attenuated degradation of the microelectronics fabrication.Type: GrantFiled: November 19, 1999Date of Patent: March 11, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Mei Sheng Zhou, Vincent Sih, Simon Chooi, Zainab Bte Ismail, Ping Yu Ee, Sang Yee Loong
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Publication number: 20030006462Abstract: A semiconductor device is provided having angled dopant implantation and vertical trenches in the silicon on insulator substrate adjacent to the sides of a semiconductor gate. A second dopant implantation is in the exposed the source/drain junctions. Contacts having inwardly curved cross-sectional widths in the semiconductor substrate connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.Type: ApplicationFiled: August 23, 2002Publication date: January 9, 2003Inventors: Shyue Fong Quek, Ting Cheong Ang, Sang Yee Loong, Puay Ing Ong
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Patent number: 6495399Abstract: A semiconductor chip device package comprised of a semiconductor substrate having semiconductor devices formed on the semiconductor substrate. At least one dielectric layer is over the semiconductor substrate. At least one layer of interconnects is over the semiconductor devices and within the at least one respective dielectric layer with at least a portion of the interconnects being separated by voids having a vacuum or air therein. A passivation layer is over the uppermost of the at least one layer of interconnects. Wherein the semiconductor chip device is vacuum sealed within a semiconductor chip device package.Type: GrantFiled: November 1, 1999Date of Patent: December 17, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Shyue-Fong Quek, Ting Cheong Ang, Duay Ing Ong, Sang Yee Loong
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Patent number: 6492726Abstract: In accordance with the objectives of the invention a new package is provided that is provided with a cavity that is shaped such that more than one semiconductor device can in a vertical direction be mounted in the cavity of the package. The devices that are mounted inside the cavity of the package are separated by separate components of insulation, the overlying devices are electrically interconnected by horizontally positioned solder bumps and vertical interconnect plugs.Type: GrantFiled: September 22, 2000Date of Patent: December 10, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Shyue Fong Quek, Ying Keung Leung, Sang Yee Loong, Ting Cheong Ang
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Patent number: 6492242Abstract: A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures.Type: GrantFiled: July 3, 2000Date of Patent: December 10, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Alex See, Cher Liang Randall Cha, Shyuz Fong Quek, Ting Cheong Ang, Wye Boon Loh, Sang Yee Loong, Jun Song, Chua Chee Tee
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Patent number: 6486515Abstract: A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. An N-well is formed within a silicon semiconductor substrate. A P+ region is implanted within a portion of the N-well and an N+ region is implanted within a portion of the semiconductor substrate not occupied by the N-well. An oxide layer is formed overlying the semiconductor substrate and patterned to form openings to the semiconductor substrate. An epitaxial silicon layer is grown within the openings and overlying the oxide layer. Shallow trench isolation regions are formed within the epitaxial silicon layer extending to the underlying oxide layer. Gate electrodes and associated source and drain regions are formed in and on the epitaxial silicon layer between the shallow trench isolation regions. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions.Type: GrantFiled: April 24, 2002Date of Patent: November 26, 2002Assignee: Chartered Semiconductor Manufacturing LtdInventors: Song Jun, Ting Cheong Ang, Sang Yee Loong, Shyue Fong Quek
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Publication number: 20020151108Abstract: A semiconductor device and manufacturing process therefor is provided in which angled dopant implantation is followed by the formation of vertical trenches in the silicon on insulator substrate adjacent to the sides of the semiconductor gate. A second dopant implantation in the exposed the source/drain junctions is followed by a rapid thermal anneal that forms the semiconductor channel in the substrate. Contacts having inwardly curved cross-sectional widths in the semiconductor substrate are then formed which connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.Type: ApplicationFiled: June 10, 2002Publication date: October 17, 2002Inventors: Shyue Fong Quek, Ting Cheong Ang, Sang Yee Loong, Puay Ing Ong