Abstract: A clock distribution circuit includes a global distribution circuit, a first local distribution circuit and a second local distribution circuit. The global distribution circuit receives external clock signals and generates internal clock signals and primary reference clock signal set according to the external clock signals. The first local distribution circuit receives the internal clock signals and the primary reference clock signal set and generates a secondary reference clock signal set according to the internal clock signals and the primary reference clock signal set. The second local distribution circuit receives the internal clock signals and the secondary reference clock signal set and generates a thirdly reference clock signal set according to the internal clock signals and the secondary reference clock signal set.

Abstract: A clock distribution circuit includes a global distribution circuit, a first local distribution circuit and a second local distribution circuit. The global distribution circuit receives external clock signals and generates internal clock signals and primary reference clock signal set according to the external clock signals. The first local distribution circuit receives the internal clock signals and the primary reference clock signal set and generates a secondary reference clock signal set according to the internal clock signals and the primary reference clock signal set. The second local distribution circuit receives the internal clock signals and the secondary reference clock signal set and generates a thirdly reference clock signal set according to the internal clock signals and the secondary reference clock signal set.

Abstract: Devices for reducing power consumption and skew for transmission of signals in a clock distribution circuit are described. A global distribution circuit is configured to divide external clock signals to generate first divided multiphase clock signals and divide one of the first divided multiphase clock signals to generate a reference clock signal. A local distribution circuit is configured to generate second divided multiphase clock signals according to a portion of the first divided multiphase clock signals and the reference clock signal.

Abstract: Devices for reducing power consumption and skew for transmission of signals in a clock distribution circuit are described. A global distribution circuit is configured to divide external clock signals to generate first divided multiphase clock signals and divide one of the first divided multiphase clock signals to generate a reference clock signal. A local distribution circuit is configured to generate second divided multiphase clock signals according to a portion of the first divided multiphase clock signals and the reference clock signal.

Abstract: A receiving circuit includes a clock input portion configured to buffer a first pattern signal and configured to retard the buffered first pattern signal by a first delay time to generate an input clock signal, a data input portion configured to buffer a second pattern signal and configured to retard the buffered second pattern signal by a second delay time to generate an input data signal, and a comparator configured to compare a phase of the input clock signal with a phase of the input data signal to generate a comparison signal for adjusting the second delay time.

Abstract: A semiconductor device includes a sampling unit suitable for sampling a logic value of an input signal based on an edge of an operation clock to output a sampling signal, an edge detection unit suitable for detecting an edge of the input signal based on the sampling signal, and a phase control unit suitable for controlling a phase of the operation clock while periodically changing a value of a clock delay code at each predetermined period and substituting a code value, which is obtained by calculating a value of the clock delay code corresponding to a time point at which an operation of the edge detection unit is completed and a value of a pre-phase code determined based on the sampling signal, for the clock delay code.

Abstract: A buffer circuit includes an amplification unit configured to amplify and output a difference between an input signal and a reference voltage; and a driver configured to drive an output node in response to the output of the amplification unit and be controlled in at least one of a pull-up driving strength and a pull-down driving strength at the output node in response to the reference voltage.

Abstract: A receiving circuit includes a clock input portion configured to buffer a first pattern signal and configured to retard the buffered first pattern signal by a first delay time to generate an input clock signal, a data input portion configured to buffer a second pattern signal and configured to retard the buffered second pattern signal by a second delay time to generate an input data signal, and a comparator configured to compare a phase of the input clock signal with a phase of the input data signal to generate a comparison signal for adjusting the second delay time.

Abstract: A receiver circuit of a semiconductor apparatus includes a first sense amplifier, a level restriction unit, and a second sense amplifier. The first sense amplifier amplifies an input signal in response to a clock signal and generates a first signal with a voltage swing between a first level and a second level. The level restriction unit receives the first signal and generates a correction signal with a voltage swing between the first level and a third level. The second sense amplifier amplifies the correction signal in response to the clock signal and generates a second signal with the voltage swing between the first level and the second level.

Abstract: A buffer circuit includes an amplification unit configured to amplify and output a difference between an input signal and a reference voltage; and a driver configured to drive an output node in response to the output of the amplification unit and be controlled in at least one of a pull-up driving strength and a pull-down driving strength at the output node in response to the reference voltage.

Abstract: A clock data recovery (CDR) circuit occupies a small area required in a high-integration semiconductor device, electronic device and system and is easy in design modification. The CDR circuit includes a digital filter configured to filter phase comparison result signals received during predetermined periods and output control signals, a driver configured to control the digital filter by adjusting the predetermined periods, and an input/output circuit configured to recognize an input and output of data and clock in response to the control signals.

Abstract: Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

Abstract: Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

Abstract: A receiver circuit of a semiconductor apparatus includes a first sense amplifier, a level restriction unit, and a second sense amplifier. The first sense amplifier amplifies an input signal in response to a clock signal and generates a first signal with a voltage swing between a first level and a second level. The level restriction unit receives the first signal and generates a correction signal with a voltage swing between the first level and a third level. The second sense amplifier amplifies the correction signal in response to the clock signal and generates a second signal with the voltage swing between the first level and the second level.

Abstract: A semiconductor device includes a plurality of CML buffering units configured to buffer, in parallel, a plurality of serially applied data signals to CML levels in a sequence responding to multi-phase source clocks; and a CMOS amplification block configured to amplify a plurality of buffered data signals, sequentially outputted from the plurality of CML buffering units, to CMOS levels in response to the multi-phase source clocks, and output amplified data signals in parallel at the same timing.

Abstract: Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

Abstract: Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

Abstract: A semiconductor device includes a plurality of CML buffering units configured to buffer, in parallel, a plurality of serially applied data signals to CML levels in a sequence responding to multi-phase source clocks; and a CMOS amplification block configured to amplify a plurality of buffered data signals, sequentially outputted from the plurality of CML buffering units, to CMOS levels in response to the multi-phase source clocks, and output amplified data signals in parallel at the same timing.

Abstract: Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

Abstract: A semiconductor memory device can a desired internal clock in consideration of a delay time of an actual clock/data path. The semiconductor memory device includes a multiclock signal generating unit configured to receive a reference clock signal and generate a plurality of clock signals having a constant phase difference from each other, a delay modeling unit configured to generate a plurality of delay clock signals by reflecting a delay time of an actual clock/data path to the plurality of clock signals, a selection signal generating unit configured to generate selection signals by comparing phases between the reference clock signal and the plurality of delay clock signals, and a phase multiplexing unit configured to output any one of the plurality of clock signals as a final clock signal in response to the selection signals.