Abstract: Time delay devices for producing tunable time delays in optical signals. Cascades of the time delay devices can be used for beam steering in phased-array antennas. The time delay may be produced by selecting a time delay between an input and output of the time delay device from any of the time delay obtained by all four-port switches of the time delay device being in an OFF state and time delays obtainable by switching any one of the four-port switches to an ON state; and producing the selected time delay between the input and output of the time delay device by performing any of avoiding an application of an electrical control signal to any of electro-optic switch elements of the time delay device and applying the electrical control signal to one of the electro-optic switch elements that corresponds to a four-port coupler corresponding to the selected time delay.

Abstract: An integrated circuit field effect transistor includes contact pads which are separated by sidewall spacers. A first pad which electrically contacts one of the spaced-apart source and drain regions extends onto the gate electrode top, to define a first pad sidewall on the gate electrode top. A first capping layer on the first pad defines a first capping layer sidewall on the first pad. A first insulating sidewall spacer is formed on the first pad sidewall and on the first capping layer sidewall. A second pad, electrically contacting the other of the source and drain regions, extends onto the gate electrode top and contacts the first insulating sidewall spacer. A second capping layer may be formed on the second pad, opposite the substrate, to define a second capping layer sidewall on the first capping layer. A second insulating sidewall spacer may be formed on the second pad sidewall and on the second capping layer sidewall.

Abstract: An integrated circuit field effect transistor includes contact pads which are separated by sidewall spacers. A first pad which electrically contacts one of the spaced-apart source and drain regions extends onto the gate electrode top, to define a first pad sidewall on the gate electrode top. A first capping layer on the first pad defines a first capping layer sidewall on the first pad. A first insulating sidewall spacer is formed on the first pad sidewall and on the first capping layer sidewall. A second pad, electrically contacting the other of the source and drain regions, extends onto the gate electrode top and contacts the first insulating sidewall spacer. A second capping layer may be formed on the second pad, opposite the substrate, to define a second capping layer sidewall on the first capping layer. A second insulating sidewall spacer may be formed on the second pad sidewall and on the second capping layer sidewall.