Patents by Inventor Sang Yeon Kim

Sang Yeon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8680741
    Abstract: A haptic actuator using a cellulose electro-active paper film is provided. The haptic actuator includes a cellulose electro-active paper film exhibiting a piezoelectric phenomenon and a metal electrode for applying electricity to the electro-active paper film, so that the haptic actuator can be provided in the form of a thin film, can manifest high transparency, and can produce displacement to the magnitude of sufficiently stimulating the sensor receptors of a user's skin in response to the applied electricity. Also, the haptic actuator is friendly to the environment and humans thanks to the use of cellulose which is an environmentally friendly material.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: March 25, 2014
    Assignee: Industry Collaboration Foundation of Korea University of Technology and Education
    Inventors: Sang-Yeon Kim, Jae hwan Kim
  • Publication number: 20130314594
    Abstract: Disclosed herein is a method and apparatus for converting a film image (e.g., a movie) into a television (TV) image. In the method and apparatus for converting the film image into a TV image, a pull-down field is added based on header information of a TV interface if BT601, BT656 and BT1120 are used as standards for the TV interface, thereby improving accuracy and reducing load of the apparatus upon conversion of the film image into the TV image. The apparatus includes a film image reception unit which receives a film image; a header information checking unit which checks header information of the film image; and an image conversion unit which uses the header information checked by the header information checking unit to convert the film image into the TV image.
    Type: Application
    Filed: May 22, 2013
    Publication date: November 28, 2013
    Applicant: CORE LOGIC INC.
    Inventor: Sang Yeon KIM
  • Patent number: 8420551
    Abstract: Example methods and example embodiments include methods of fabricating semiconductor devices and semiconductor devices fabricated by the same. Example fabricating methods include forming a first nanowire, oxidizing the first nanowire to form a first nanostructure including a first insulator and a second nanowire, and oxidizing the second nanowire to form a second nanostructure including a second insulator and nanodots. Example semiconductor devices include nanostructures including nanodots and nanostructures providing storage nodes in memory devices.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: April 16, 2013
    Assignees: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation
    Inventors: Myung-Jong Kim, In-Seok Yeo, Dae-Hong Ko, Hyun-Chul Sohn, Mann-Ho Cho, Sang-Yeon Kim
  • Publication number: 20130088739
    Abstract: A method of setting printing options at a host apparatus using a LINUX-based operation system (OS), the method including displaying at least one printing option providing text input for a user from among printing options provided by an image forming apparatus connected to the host apparatus; receiving setting information regarding printing options selected by a user from among the at least one printing option as text input; and storing the setting information with the corresponding printing options.
    Type: Application
    Filed: August 21, 2012
    Publication date: April 11, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-yeon KIM, In-sung Choi
  • Publication number: 20120298954
    Abstract: There are provided a semiconductor light emitting device and a manufacturing method of the same. The semiconductor light emitting device includes a light emitting structure including first and second conductive semiconductor layers with an active layer interposed therebetween; first and second bonding electrodes connected to the first and second conductive semiconductor layers, respectively; a transparent electrode layer formed on the second conductive semiconductor layer; a plurality of nano structures formed on the transparent electrode layer; and a passivation layer formed to cover the plurality of nano-structures, wherein refractive indexes of the transparent electrode layer, the plurality of nano-structures, and the passivation layer may be sequentially reduced.
    Type: Application
    Filed: May 24, 2012
    Publication date: November 29, 2012
    Inventors: Sang Yeon KIM, Jong Rak Sohn, Gi Bum Kim, Su Yeol Lee, Yong II Kim
  • Publication number: 20120161587
    Abstract: A haptic actuator using a cellulose electro-active paper film is provided. The haptic actuator includes a cellulose electro-active paper film exhibiting a piezoelectric phenomenon and a metal electrode for applying electricity to the electro-active paper film, so that the haptic actuator can be provided in the form of a thin film, can manifest high transparency, and can produce displacement to the magnitude of sufficiently stimulating the sensor receptors of a user's skin in response to the applied electricity. Also, the haptic actuator is friendly to the environment and humans thanks to the use of cellulose which is an environmentally friendly material.
    Type: Application
    Filed: November 14, 2011
    Publication date: June 28, 2012
    Applicant: INDUSTRY COLLABORATION FOUNDATION OF KOREA UNIVERSITY OF TECHNOLOGY AND EDUCATION
    Inventors: Sang yeon KIM, Jae hwan KIM
  • Publication number: 20110165761
    Abstract: Example methods and example embodiments include methods of fabricating semiconductor devices and semiconductor devices fabricated by the same. Example fabricating methods include forming a first nanowire, oxidizing the first nanowire to form a first nanostructure including a first insulator and a second nanowire, and oxidizing the second nanowire to form a second nanostructure including a second insulator and nanodots. Example semiconductor devices include nanostructures including nanodots and nanostructures providing storage nodes in memory devices.
    Type: Application
    Filed: December 6, 2010
    Publication date: July 7, 2011
    Inventors: Myung-Jong KIM, In-Seok Yeo, Dae-Hong Ko, Hyun-Chul Sohn, Mann-Ho Cho, Sang-Yeon Kim
  • Patent number: 7665259
    Abstract: Disclosed herein is a built-up type box-shaped steel column for filling concrete therein, that can be formed easily and economically in a built-up scheme by using ?-beams and steel plates, and a method for manufacturing the same that includes bonding a steel plate at the inner surface of a ?-shapes during a process of making a built-up type box-shaped steel column, thereby having a good resistance against a lateral pressure of concrete filled in the steel column and preventing the bonded portion from being exposed to the outside to provide a better outer appearance. The built-up type box-shaped steel column for filling concrete therein, includes: a ?-shapes disposed at each of the four corners of a box-shaped steel column to be formed; and a steel plate disposed between the ?-shapes adjacent to each other for connecting the ?-shapes with each other.
    Type: Grant
    Filed: December 6, 2005
    Date of Patent: February 23, 2010
    Assignees: Korea National Housing Corporation, SH Corporation, Myong HWA Engineering Co., Ltd., Sen Structural Engineers Co., Ltd.
    Inventors: Young-Ho Yoon, Sang-Yeon Kim, Su-Jin Lee, Hyung-Geun Kim, Chang-Shin Lee, Soon-Woo Nam, Seok-Tae Kang, Chang-Nam Lee, Sung-Bae Kim
  • Publication number: 20070296054
    Abstract: A fuse is formed by a borderless contact process that removes the silicon nitride layer above the cutting region of the fuse. The fuse is formed on a semiconductor substrate, and comprises an insulation layer such as an oxide layer formed on the substrate, a fuse layer formed on the insulation layer, where the fuse layer includes at least a first region and a second region, and a silicon nitride layer formed only above the first region of the fuse layer. The first region of the fuse layer is where contact holes are formed for applying electrical stress to the fuse, and the second region of the fuse layer is where the fuse is cut in response to electrical stress applied to the fuse. Because the silicon nitride layer is removed above the second region of the fuse layer, the silicon nitride layer does not inhibit the cutting of the fuse in response to electrical stress applied to the fuse.
    Type: Application
    Filed: June 27, 2006
    Publication date: December 27, 2007
    Inventor: Sang Yeon Kim
  • Patent number: 7259071
    Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: August 21, 2007
    Assignee: SilTerra Malaysia Sdn.Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Chiew Sin Ping, Wan Gie Lee, Choong Shiau Chien, Zadig Lam, Hitomi Watanabe, Naoto Inoue
  • Patent number: 7241665
    Abstract: A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a trench having a first slope and a second slope. The first slope is greater than 45 degrees, and the second slope is less than 45 degrees. The trench is filled to form the isolation structure.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: July 10, 2007
    Assignee: SilTerra Malaysia Sdn. Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ch'ng Toh Ghee, Ramakrishnan Rajagopal, Chiew Sin Ping, Wan Gie Lee, Choong Shiau Chien, Charlie Tay, Chang Gi Lee, Hitomi Watanabe, Naoto Inoue
  • Patent number: 7208378
    Abstract: A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: April 24, 2007
    Assignee: Silterra
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ong Boon Teong, Oh Choong Young, Ng Chun Leng, Joung Joon Ho
  • Patent number: 7166901
    Abstract: A semiconductor device comprises a semiconductor substrate having a high voltage region and a low voltage region, at least a pair of adjacent high voltage MOS transistors disposed on the high voltage region of the semiconductor substrate, and low voltage MOS transistors disposed on the low voltage region of the semiconductor substrate. A first element isolator comprises a first shallow trench disposed on a surface of the low voltage, region of the semiconductor substrate, and a first dielectric embedded in the first shallow trench. A pair of second element isolators comprises two second shallow trenches spaced apart at an interval between a source region or a drain region of the pair of the adjacent high voltage MOS transistors and a source or a drain region of the other of the pair of the adjacent high voltage MOS transistors, and a second dielectric embedded in each of the second shallow trenches.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: January 23, 2007
    Assignees: Seiko Instruments Inc., Silterra Malaysia Sdh. Bhd
    Inventors: Naoto Inoue, Hitomi Sakurai, Min Paek, Sang Yeon Kim, In Ki Kim
  • Patent number: 7152087
    Abstract: A filter, in particular, a finite impulse response (FIR) filter having a variable data input and output rate is disclosed. The FIR filter includes a first-in first-out (FIFO) architectural buffer, an address generator for circularly generating respective addresses for FIFO of data items and providing the addresses to the buffer, a filter for performing filtering on data items having different rates, which are input from the buffer, and outputting one or more data, and a controller for controlling address generation of the address generator and controlling transfer paths of data items for filtering of the filter. It is possible to variably control the input and output rate of filtering data by the FIR filter.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: December 19, 2006
    Assignee: LG Electronics Inc.
    Inventors: Jong In Choi, Sang Yeon Kim, Dong Il Han
  • Patent number: 7091104
    Abstract: A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a trench having a first slope and a second slope. The first slope is greater than 45 degrees, and the second slope is less than 45 degrees. The trench is filled to form the isolation structure.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: August 15, 2006
    Assignee: SilTerra Malaysia Sdn. Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ch'ng Toh Ghee, Ramakrishnan Rajagopal, Chiew Gie Lee, Wan Gie Lee, Choong Shiau Chien, Charlie Tay, Chang Gi Lee, Hitomi Watanabe, Naoto Inoue
  • Publication number: 20060117704
    Abstract: Disclosed herein is a built-up type box-shaped steel column for filling concrete therein, that can be formed easily and economically in a built-up scheme by using ?-beams and steel plates, and a method for manufacturing the same that includes bonding a steel plate at the inner surface of a ?-shapes during a process of making a built-up type box-shaped steel column, thereby having a good resistance against a lateral pressure of concrete filled in the steel column and preventing the bonded portion from being exposed to the outside to provide a better outer appearance. The built-up type box-shaped steel column for filling concrete therein, includes: a ?-shapes disposed at each of the four corners of a box-shaped steel column to be formed; and a steel plate disposed between the ?-shapes adjacent to each other for connecting the ?-shapes with each other.
    Type: Application
    Filed: December 6, 2005
    Publication date: June 8, 2006
    Inventors: Young-Ho Yoon, Sang-Yeon Kim, Su-Jin Lee, Hyung-Geun Kim, Chang-Shin Lee, Soon-Woo Nam, Seok-Tae Kang, Chang-Nam Lee, Sung-Bae Kim
  • Patent number: 6987893
    Abstract: Disclosed is an image interpolation method and apparatus thereof. The present invention includes the steps of searching an edge direction to be used for interpolation by a pixel matching using input pixels and generating a pixel to be substantially interpolated by referring to pixels located on the searched edge direction. The present invention includes the steps of carrying out a first interpolation on input pixels using linear interpolation and finding weighted value coefficients in accordance with a relationship between the first interpolated pixel and the adjacent input pixels to be used for interpolation and preparing a pixel to be substantially interpolated by adaptive weighted interpolation applying the found weighted value coefficient to the adjacent input pixels. Accordingly, the present invention minimizes the blurring and is free of geometrical distortion.
    Type: Grant
    Filed: January 4, 2002
    Date of Patent: January 17, 2006
    Assignee: LG Electronics Inc.
    Inventor: Sang Yeon Kim
  • Patent number: 6898255
    Abstract: An apparatus and method for generating finite impulse response (FIR) filter coefficients are presented. The apparatus includes an address generator that multiplies a desired cutoff frequency f by an integer n to generate an address, a first look-up table that generates a sine function value of the address, a divider that divides the sine function value by n*pi, a multiplexer that generates an impulse response function value by selecting one of a value produced from the divider and 2*f based on an outside control signal, and a multiplier that multiplies the impulse response function value by a corresponding window function value to generate an nth filter coefficient for the FIR filter.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: May 24, 2005
    Assignee: LG Electronics Inc.
    Inventor: Sang Yeon Kim
  • Patent number: 6890822
    Abstract: A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: May 10, 2005
    Assignee: SilTerra Malaysia Sdn. Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ong Boon Teong, Oh Choong Young, Ng Chun Leng, Joung Joon Ho
  • Patent number: 6818514
    Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: November 16, 2004
    Assignee: SilTerra Malaysia Sdn. Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Chiew Sin Ping, Wan Gie Lee, Choong Shiau Chien, Zadig Lam, Hitomi Watanabe, Naoto Inoue