Patents by Inventor Sang-Yeop BAECK
Sang-Yeop BAECK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10431272Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.Type: GrantFiled: March 15, 2018Date of Patent: October 1, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-yeop Baeck, Siddharth Gupta, In-hak Lee, Jae-seung Choi, Tae-hyung Kim, Dae-young Moon, Dong-wook Seo
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Patent number: 10424577Abstract: A semiconductor device including memory cell transistors on a substrate is provided. The semiconductor device includes a first wiring layer on the memory cell transistors and including a bit line and a first conductive pattern, a second wiring layer on the first wiring layer and including a ground line, a first via interposed between and electrically connecting the bit line and a source/drain of a first memory cell transistor among the memory cell transistors, and a first extended via interposed between the ground line and a source/drain of a second memory cell transistor among the memory cell transistors. The ground line is electrically connected to the source/drain of the second memory cell transistor through the first extended via and the first conductive pattern. The first extended via has a width greater than that of the first via.Type: GrantFiled: December 15, 2017Date of Patent: September 24, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Inhak Lee, Sang-Yeop Baeck, JaeSeung Choi, Hyunsu Choi, SangShin Han
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Publication number: 20190164596Abstract: A memory device includes a memory cell array and a peripheral circuit. The memory cell array receives a first power supply voltage and includes a plurality of bit cells that store data based on the first power supply voltage. The peripheral circuit is receives a second power supply voltage and controls the memory cell array based on the second power supply voltage. The peripheral circuit includes a voltage generation circuit that receives the first power supply voltage and the second power supply voltage. The voltage generation circuit adaptively adjusts a word-line driving voltage directly or indirectly based on a difference between the first power supply voltage and the second power supply voltage during a memory operation on the plurality of bit cells, and applies the word-line driving voltage to a first word-line coupled to first bit cells selected from the bit cells.Type: ApplicationFiled: September 11, 2018Publication date: May 30, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: In-Hak LEE, Sang-Yeop Baeck, Jae-Seung Choi
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Publication number: 20190080736Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.Type: ApplicationFiled: March 15, 2018Publication date: March 14, 2019Inventors: Sang-yeop Baeck, Siddharth Gupta, In-hak Lee, Jae-seung Choi, Tae-hyung Kim, Dae-young Moon, Dong-wook Seo
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Publication number: 20180294256Abstract: A semiconductor device including memory cell transistors on a substrate is provided. The semiconductor device includes a first wiring layer on the memory cell transistors and including a bit line and a first conductive pattern, a second wiring layer on the first wiring layer and including a ground line, a first via interposed between and electrically connecting the bit line and a source/drain of a first memory cell transistor among the memory cell transistors, and a first extended via interposed between the ground line and a source/drain of a second memory cell transistor among the memory cell transistors. The ground line is electrically connected to the source/drain of the second memory cell transistor through the first extended via and the first conductive pattern. The first extended via has a width greater than that of the first via.Type: ApplicationFiled: December 15, 2017Publication date: October 11, 2018Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Inhak LEE, Sang-Yeop BAECK, JaeSeung CHOI, Hyunsu CHOI, SangShin HAN
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Publication number: 20180294018Abstract: A memory device includes a first write assist circuit providing a cell voltage or a write assist voltage to a first memory cell connected with a first bit line pair, a first write driver that provides write data to the first memory cell through the first bit line pair, a second write assist circuit that provides the cell voltage or the write assist voltage to a second memory cell connected with a second bit line pair, and a second write driver that provides write data to the second memory cell through the second bit line pair. One of the first and second write assist circuits provides the write assist voltage in response to a column selection signal for selecting one write driver, which provides write data, from among the first, and second write drivers, and the other thereof provides the cell voltage in response to the column selection signal.Type: ApplicationFiled: December 13, 2017Publication date: October 11, 2018Inventors: Sang-Yeop Baeck, Inhak Lee, SangShin Han, Tae-Hyung Kim, JaeSeung Choi, Sunghyun Park, Hyunsu Choi
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Publication number: 20180294219Abstract: Provided is an integrated circuit which includes: a plurality of conductive lines extending in a first horizontal direction on a plane separate from a gate line, and including first and second conductive lines; a source/drain contact having a bottom surface connected to a source/drain region, and including a lower source/drain contact and an upper source/drain contact which are connected to each other in a vertical direction; and a gate contact having a bottom surface connected to the gate line, and extending in the vertical direction, in which the upper source/drain contact is placed below the first conductive line, and the gate contact is placed below the second conductive line. A top surface of the lower source/drain contact may be larger than a bottom surface of the upper source/drain contact.Type: ApplicationFiled: March 1, 2018Publication date: October 11, 2018Inventors: Tae-hyung Kim, Jung-ho Do, Dae-young Moon, Sang-yeop Baeck, Jae-hyun Lim, Jae-seung Choi, Sang-shin Han
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Patent number: 9886997Abstract: A semiconductor device for reducing an instantaneous voltage drop is provided. The semiconductor device includes a first power line configured to provide a first power supply voltage and a first power transistor connected between the first power line and a first logic transistor. The first power transistor includes a first source or drain connected to the first power line, a gate receiving a power gating control signal, and a second source or drain connected to a first source or drain of the first logic transistor using a shared semiconductor junction.Type: GrantFiled: March 23, 2017Date of Patent: February 6, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae Hyung Kim, Sang Yeop Baeck, Jae Young Kim, Jin Sung Kim
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Publication number: 20170221554Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.Type: ApplicationFiled: January 27, 2017Publication date: August 3, 2017Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Yeop BAECK, Tae-Hyung KIM, Daeyoung MOON, Dong-Wook SEO, Inhak LEE, Hyunsu CHOI, Taejoong SONG, Jae-Seung CHOI, Jung-Myung KANG, Hoon KIM, Jisu YU, Sun-Yung JANG
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Publication number: 20170194041Abstract: A semiconductor device for reducing an instantaneous voltage drop is provided. The semiconductor device includes a first power line configured to provide a first power supply voltage and a first power transistor connected between the first power line and a first logic transistor. The first power transistor includes a first source or drain connected to the first power line, a gate receiving a power gating control signal, and a second source or drain connected to a first source or drain of the first logic transistor using a shared semiconductor junction.Type: ApplicationFiled: March 23, 2017Publication date: July 6, 2017Inventors: TAE HYUNG KIM, SANG YEOP BAECK, JAE YOUNG KIM, JIN SUNG KIM
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Patent number: 9627037Abstract: A semiconductor device for reducing an instantaneous voltage drop is provided. The semiconductor device includes a first power line configured to provide a first power supply voltage and a first power transistor connected between the first power line and a first logic transistor. The first power transistor includes a first source or drain connected to the first power line, a gate receiving a power gating control signal, and a second source or drain connected to a first source or drain of the first logic transistor using a shared semiconductor junction.Type: GrantFiled: December 22, 2015Date of Patent: April 18, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae Hyung Kim, Sang Yeop Baeck, Jae Young Kim, Jin Sung Kim
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Publication number: 20160189759Abstract: A semiconductor device for reducing an instantaneous voltage drop is provided. The semiconductor device includes a first power line configured to provide a first power supply voltage and a first power transistor connected between the first power line and a first logic transistor. The first power transistor includes a first source or drain connected to the first power line, a gate receiving a power gating control signal, and a second source or drain connected to a first source or drain of the first logic transistor using a shared semiconductor junction.Type: ApplicationFiled: December 22, 2015Publication date: June 30, 2016Inventors: TAE HYUNG KIM, SANG YEOP BAECK, JAE YOUNG KIM, JIN SUNG KIM
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Patent number: 8947951Abstract: A semiconductor memory device includes at least one memory cell connected to an internal voltage line that receives a cell power supply voltage and a write assist circuit connected to the internal voltage line. The write assist circuit lowers a level of the cell power supply voltage to a target level during a first period of a write operation on the memory cell and maintains the level of the cell power supply voltage at the target level during a second period of the write operation based on a write assist control signal. The second period succeeds the first period.Type: GrantFiled: March 15, 2013Date of Patent: February 3, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Yeop Baeck, Jin-Sung Kim, Jang-Hwan Yoon
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Patent number: 8884687Abstract: A power gating circuit includes a first current switch, a second current switch, and a switching controller. The first current switch is connected between a power rail and a circuit block operated by an operating supply voltage, and provides a first current when turned on. The second current switch is connected between the power rail and circuit block, and provides a second current larger than the first current when turned on. The switching controller turns on first current switch when transitioned from a sleep mode to an active mode to change the operating supply voltage using the first current, generates a reference voltage based on the operating supply voltage that changes more slowly than the operating supply voltage, and turns on the second current switch based on the reference voltage to provide the second current to the circuit block.Type: GrantFiled: April 22, 2013Date of Patent: November 11, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jang-Hwan Yoon, Jin-Sung Kim, Sang-Yeop Baeck
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Publication number: 20140015590Abstract: A power gating circuit includes a first current switch, a second current switch, and a switching controller. The first current switch is connected between a power rail and a circuit block operated by an operating supply voltage, and provides a first current when turned on. The second current switch is connected between the power rail and circuit block, and provides a second current larger than the first current when turned on. The switching controller turns on first current switch when transitioned from a sleep mode to an active mode to change the operating supply voltage using the first current, generates a reference voltage based on the operating supply voltage that changes more slowly than the operating supply voltage, and turns on the second current switch based on the reference voltage to provide the second current to the circuit block.Type: ApplicationFiled: April 22, 2013Publication date: January 16, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jang-Hwan YOON, Jin-Sung Kim, Sang-Yeop Baeck
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Publication number: 20130343135Abstract: A semiconductor memory device includes at least one memory cell connected to an internal voltage line that receives a cell power supply voltage and a write assist circuit connected to the internal voltage line. The write assist circuit lowers a level of the cell power supply voltage to a target level during a first period of a write operation on the memory cell and maintains the level of the cell power supply voltage at the target level during a second period of the write operation based on a write assist control signal. The second period succeeds the first period.Type: ApplicationFiled: March 15, 2013Publication date: December 26, 2013Applicant: SAMSUNG ELECTRONICS CO., LTDInventors: Sang-Yeop BAECK, Jin-Sung KIM, Jang-Hwan YOON