Abstract: A computer system includes a main memory device and a processor. The main memory device includes a non-volatile memory and a memory controller to control the non-volatile memory. The processor is connected to the main memory device, executes an application program loaded to the non-volatile memory, and provides the memory controller with a command including context property information of an allocation region. The memory controller receives the command and controls the non-volatile memory based on the context property information.

Abstract: A computer system includes a main memory device and a processor. The main memory device includes a non-volatile memory and a memory controller to control the non-volatile memory. The processor is connected to the main memory device, executes an application program loaded to the non-volatile memory, and provides the memory controller with a command including context property information of an allocation region. The memory controller receives the command and controls the non-volatile memory based on the context property information.

Abstract: A computer system includes a main memory device and a processor. The main memory device includes a non-volatile memory and a memory controller to control the non-volatile memory. The processor is connected to the main memory device, executes an application program loaded to the non-volatile memory, and provides the memory controller with a command including context property information of an allocation region. The memory controller receives the command and controls the non-volatile memory based on the context property information.

Abstract: A computer system includes a main memory device and a processor. The main memory device includes a non-volatile memory and a memory controller to control the non-volatile memory. The processor is connected to the main memory device, executes an application program loaded to the non-volatile memory, and provides the memory controller with a command including context property information of an allocation region. The memory controller receives the command and controls the non-volatile memory based on the context property information.

Abstract: A memory system processing data according to a received first request may include a main memory and a memory controller. The main memory may comprise a first area and a second area, and may be configured to provide data from the first area to the second area. The memory controller may comprise a scoreboard configured to indicate that a first piece of sub-data of a first set of sub-data of the data has been provided from the first area to the second area. Based on the scoreboard, the memory controller may be configured to perform processing of the first request by using the first piece of sub-data before providing of other pieces of sub-data of the first set of sub-data from the first area to the second area is completed.

Abstract: A memory system processing data according to a received first request may include a main memory and a memory controller. The main memory may comprise a first area and a second area, and may be configured to provide data from the first area to the second area. The memory controller may comprise a scoreboard configured to indicate that a first piece of sub-data of a first set of sub-data of the data has been provided from the first area to the second area. Based on the scoreboard, the memory controller may be configured to perform processing of the first request by using the first piece of sub-data before providing of other pieces of sub-data of the first set of sub-data from the first area to the second area is completed.

Abstract: A cache memory system includes a cache memory that includes a first memory portion and a flexible buffer memory portion. A cache controller is coupled to the cache memory and is configured to control allocation and/or deallocation of blocks from the first memory portion to and/or from the flexible buffer memory portion.

Abstract: A memory controller may reduce bus utilization time. The memory controller may include a main controller, a data reading unit, and a serial interface. The main controller may store a control data signal received from a processor through a bus, and may control a memory by generating a request data signal, which may be based on the stored control data signal. The data reading unit may store read address signals, which may be received from at least one of the processor and IP blocks through another bus, and may read data from the memory by generating a command data signal, which may be based on the stored read address signal. The serial interface may interface at least one of the main controller and the data reading unit with the memory. The memory controller may reduce the utilization time of a bus by more efficiently controlling data reading and/or writing operations of the memory.

Abstract: Provided are a memory controller with data read-modify-write function, and a system-on-chip (SOC) having such a memory controller, where the memory controller is connected to a memory, the memory controller is connected to IP (intellectual property) blocks and a microprocessor via a system bus, and, in response to one of read, write, and modify request signals received from the one of the IP blocks or the microprocessor and an address signal, the memory controller reads a data signal from the memory, writes a write data signal to the memory, or modifies the data signal read from the memory and writes the modified data signal to the memory such that the memory controller and the SOC can reduce occupation time for the system bus and access time for the memory and additionally reduce unnecessary power consumption.

Abstract: An apparatus for testing an on-chip ROM and a method thereof are provided. By embedding the on-chip ROM test apparatus in a semiconductor chip and externally providing only minimal information, the apparatus and the method can prevent the possible exposure of ROM data stored in the ROM. Also, according to the apparatus and method, information related to the ROM address at which an error occurred can be provided together with the test result and by feeding the ROM address information back to the manufacturing process, product yield can be improved.

Abstract: Provided are a memory controller with data read-modify-write function, and a system-on-chip (SOC) having such a memory controller, where the memory controller is connected to a memory, the memory controller is connected to IP (intellectual property) blocks and a microprocessor via a system bus, and, in response to one of read, write, and modify request signals received from the one of the IP blocks or the microprocessor and an address signal, the memory controller reads a data signal from the memory, writes a write data signal to the memory, or modifies the data signal read from the memory and writes the modified data signal to the memory such that the memory controller and the SOC can reduce occupation time for the system bus and access time for the memory and additionally reduce unnecessary power consumption.

Abstract: A memory controller may reduce bus utilization time. The memory controller may include a main controller, a data reading unit, and a serial interface. The main controller may store a control data signal received from a processor through a bus, and may control a memory by generating a request data signal, which may be based on the stored control data signal. The data reading unit may store read address signals, which may be received from at least one of the processor and IP blocks through another bus, and may read data from the memory by generating a command data signal, which may be based on the stored read address signal. The serial interface may interface at least one of the main controller and the data reading unit with the memory. The memory controller may reduce the utilization time of a bus by more efficiently controlling data reading and/or writing operations of the memory.

Abstract: A cache is provided which has low power dissipation. An execution engine generates a sequential fetch signal indicating that data required at a next cycle is stored at a next location of just previously used data. A line reuse buffer is provided which stores data that is stored in a data memory of the cache and is in the same cache line as data just previously used by the execution engine. In the case where the sequential fetch signal is received and data required according to a memory request signal is stored in the same cache line of the data memory as the just previously used data, a cache controller fetches data from the line reuse buffer and controls the cache so as to stay in a stand-by mode.

Abstract: A cache memory system includes a cache memory that includes a first memory portion and a flexible buffer memory portion. A cache controller is coupled to the cache memory and is configured to control allocation and/or deallocation of blocks from the first memory portion to and/or from the flexible buffer memory portion.

Abstract: In an apparatus for testing an on-chip ROM and a method thereof, an on-chip ROM comprises a test control signal generator which, by using external test signals, including a test mode signal that sets the mode of the ROM to a test mode, a test clock signal which generates a clock used in testing the ROM, and a test reset signal for initialization, generates a ROM clock signal to operate the ROM and test control signals including a ROM address to access the ROM; a comparator which compares ROM data read from the ROM in response to the ROM address with external reference data; and a test result accumulator which, referring to the comparison result from the comparator, stores information related to whether an error exists, as a test result. If the comparison of the ROM data is performed to the last ROM address, the test result is externally output.

Abstract: A cache is provided which has low power dissipation. An execution engine generates a sequential fetch signal indicating that data required at a next cycle is stored at a next location of just previously used data. A line reuse buffer is provided which stores data that is stored in a data memory of the cache and is in the same cache line as data just previously used by the execution engine. In the case where the sequential fetch signal is received and data required according to a memory request signal is stored in the same cache line of the data memory as the just previously used data, a cache controller fetches data from the line reuse buffer and controls the cache so as to stay in a stand-by mode.