Abstract: Provided is a forceps driving apparatus including a body, a gripper installed to be received in the body and formed to be open and closed, an opening and closing member rotatably installed in the body to press or release two sides of the gripper by rotation, an elastic member connected to one side of the opening and closing member to provide an elastic force to the opening and closing member, an actuator connected to the other side of the opening and closing member to rotate the opening and closing member by contraction or extension, and a force sensing module to measure a gripping force of the gripper during the rotation of the opening and closing member.

Abstract: A wireless charging receiver as described herein includes a configurable rectifier configured to convert an alternating current input to a direct current output in a single processing stage, wherein the configurable rectifier comprises one or more diodes, and a controller communicatively coupled to the one or more diodes and configured to select one of a plurality of mode cycling schemes and control a present operating mode of the active diodes according to a selected mode cycling scheme. Additionally, an active diode as described herein includes a comparator, a gate driver, a power transistor, and a delay compensation circuit for compensation of at least one of a turn-on delay and a turn-off delay of the active diode, the delay compensation circuit including analog feedback loops.

Abstract: A resistive memory device may include a plurality of MATs, row control blocks, a plurality of word lines, a plurality of bit lines and memory cells. Each of the row control blocks may be interposed between the MATs. Each of the row control blocks may include a control element. The word lines may be arranged spaced apart from each other by a substantially uniform gap on the MATs. The bit lines may overlap with the word lines. The memory cells may be located between the word lines and the bit lines. Each of the word lines may be electrically connected with the control element of each of the row control blocks via a connection path.

Abstract: An electronic device including a semiconductor memory. The semiconductor memory may include a cell array including a plurality of resistive storage cells; a current code generation block suitable for generating a current code which has a value corresponding to an average value of current amounts of test currents respectively flowing through at least two first resistive storage cells among the plurality of resistive storage cells, in a test operation; and a sensing block suitable for comparing a read current flowing through a second resistive storage cell selected among the plurality of resistive storage cells with a reference current, and thereby sensing data of the second resistive storage cell, wherein the semiconductor memory is operable to adjust a current amount of at least one current flowing through the sensing block based on the value of the current code.

Abstract: A resistive memory device may include a plurality of MATs, row control blocks, a plurality of word lines, a plurality of bit lines and memory cells. Each of the row control blocks may be interposed between the MATs. Each of the row control blocks may include a control element. The word lines may be arranged spaced apart from each other by a substantially uniform gap on the MATs. The bit lines may overlap with the word lines. The memory cells may be located between the word lines and the bit lines. Each of the word lines may be electrically connected with the control element of each of the row control blocks via a connection path.

Abstract: A resistive memory device may include a plurality of MATs, row control blocks, a plurality of word lines, a plurality of bit lines and memory cells. Each of the row control blocks may be interposed between the MATs. Each of the row control blocks may include a control element. The word lines may be arranged spaced apart from each other by a substantially uniform gap on the MATs. The bit lines may overlap with the word lines. The memory cells may be located between the word lines and the bit lines. Each of the word lines may be electrically connected with the control element of each of the row control blocks via a connection path.

Abstract: A semiconductor system includes a first set of at least one semiconductor device, and a second set of at least one semiconductor device. The semiconductor system includes a control block for receiving an external address and providing the first and second sets of semiconductor devices with an internal address. The control block provides a semiconductor device from the first set with a first internal address corresponding to the external address, and the control block provides a semiconductor device from the second set with a second internal address that does not correspond to the external address.

Abstract: A resistive memory device may include a plurality of MATs, row control blocks, a plurality of word lines, a plurality of bit lines and memory cells. Each of the row control blocks may be interposed between the MATs. Each of the row control blocks may include a control element. The word lines may be arranged spaced apart from each other by a substantially uniform gap on the MATs. The bit lines may overlap with the word lines. The memory cells may be located between the word lines and the bit lines. Each of the word lines may be electrically connected with the control element of each of the row control blocks via a connection path.

Abstract: A semiconductor system includes a first set of at least one semiconductor device, and a second set of at least one semiconductor device. The semiconductor system includes a control block for receiving an external address and providing the first and second sets of semiconductor devices with an internal address. The control block provides a semiconductor device from the first set with a first internal address corresponding to the external address, and the control block provides a semiconductor device from the second set with a second internal address that does not correspond to the external address.

Abstract: According to one embodiment, a semiconductor memory device comprises a first bank and a second bank. Each of the first bank and the second bank comprises a memory cell having a variable resistor element, a reference cell, a sense amplifier having a first input terminal electrically coupled to the memory cell and a second input terminal electrically coupled to the reference cell, and a first transistor electrically coupling the memory cell and the first input terminal of the sense amplifier. A gate of the first transistor of the first hank and a gate of the first transistor of the second bank are independently supplied with a voltage.

Abstract: A wireless charging receiver as described herein includes a configurable rectifier configured to convert an alternating current input to a direct current output in a single processing stage, wherein the configurable rectifier comprises one or more diodes, and a controller communicatively coupled to the one or more diodes and configured to select one of a plurality of mode cycling schemes and control a present operating mode of the active diodes according to a selected mode cycling scheme, Additionally, an active diode as described herein includes a comparator, a gate driver, a power transistor, and a delay compensation circuit for compensation of at least one of a turn-on delay and a turn-off delay of the active diode, the delay compensation circuit including analog feedback loops.

Abstract: Techniques are provided to tune a gate-drive control signal for a switching device. In an aspect, a device is provided that includes a dead-time generator circuit, a first dead-time tuner circuit and a second dead-time tuner circuit. The dead-time generator circuit generates a control signal for a first switching device that is coupled to a second switching device via a switching node. The first dead-time tuner circuit generates, based on the control signal and a switching signal indicative of a voltage associated with the switching node, a first modified control signal for the first switching device. The second dead-time tuner circuit generates, based on a modified version of the switching signal and a tuning process that repeatedly modifies the control signal until a first dead-time value satisfies a defined criterion, a second modified control signal for the first switching device.

Abstract: According to one embodiment, a semiconductor memory device comprises a first bank and a second bank. Each of the first bank and the second bank comprises a memory cell having a variable resistor element, a reference cell, a sense amplifier having a first input terminal electrically coupled to the memory cell and a second input terminal electrically coupled to the reference cell, and a first transistor electrically coupling the memory cell and the first input terminal of the sense amplifier. A gate of the first transistor of the first hank and a gate of the first transistor of the second bank are independently supplied with a voltage.

Abstract: An electronic device including a semiconductor memory. The semiconductor memory may include a cell array including a plurality of resistive storage cells; a current code generation block suitable for generating a current code which has a value corresponding to an average value of current amounts of test currents respectively flowing through at least two first resistive storage cells among the plurality of resistive storage cells, in a test operation; and a sensing block suitable for comparing a read current flowing through a second resistive storage cell selected among the plurality of resistive storage cells with a reference current, and thereby sensing data of the second resistive storage cell, wherein the semiconductor memory is operable to adjust a current amount of at least one current flowing through the sensing block based on the value of the current code.

Abstract: Techniques are provided to tune a gate-drive control signal for a switching device. In an aspect, a device is provided that includes a dead-time generator circuit, a first dead-time tuner circuit and a second dead-time tuner circuit. The dead-time generator circuit generates a control signal for a first switching device that is coupled to a second switching device via a switching node. The first dead-time tuner circuit generates, based on the control signal and a switching signal indicative of a voltage associated with the switching node, a first modified control signal for the first switching device. The second dead-time tuner circuit generates, based on a modified version of the switching signal and a tuning process that repeatedly modifies the control signal until a first dead-time value satisfies a defined criterion, a second modified control signal for the first switching device.

Abstract: An electronic device including a semiconductor memory. The semiconductor memory may include a cell array including a plurality of resistive storage cells; a current code generation block suitable for generating a current code which has a value corresponding to an average value of current amounts of test currents respectively flowing through at least two first resistive storage cells among the plurality of resistive storage cells, in a test operation; and a sensing block suitable for comparing a read current flowing through a second resistive storage cell selected among the plurality of resistive storage cells with a reference current, and thereby sensing data of the second resistive storage cell, wherein the semiconductor memory is operable to adjust a current amount of at least one current flowing through the sensing block based on the value of the current code.

Abstract: An electronic device including a semiconductor memory is disclosed. The semiconductor memory includes a read path including a unit storage cell; a reference path including a unit reference cell; read circuit suitable for comparing a read current flowing on the read path with a reference current flowing on the reference path in response to a read voltage and a reference voltage, and sensing data stored in the unit storage cell based on the comparison result; a first replica path suitable for modeling the read path; and a reference voltage generation unit suitable for generating the reference voltage corresponding to a first replica current flowing on the first replica path in response to the read voltage.

Abstract: An electronic device including a semiconductor memory. The semiconductor memory may include a cell array including a plurality of resistive storage cells; a current code generation block suitable for generating a current code which has a value corresponding to an average value of current amounts of test currents respectively flowing through at least two first resistive storage cells among the plurality of resistive storage cells, in a test operation; and a sensing block suitable for comparing a read current flowing through a second resistive storage cell selected among the plurality of resistive storage cells with a reference current, and thereby sensing data of the second resistive storage cell, wherein the semiconductor memory is operable to adjust a current amount of at least one current flowing through the sensing block based on the value of the current code.

Abstract: A differential difference amplifier Type-III compensator of a voltage-mode switching converter can be designed to help regulate an input voltage from a power source. A voltage-mode switching converter can comprise a power stage and a voltage-mode controller. A voltage-mode controller can comprise a compensator, which comprises a differential difference amplifier. The design of the differential difference amplifier Type-III compensator can reduce production costs and enhance power transfer efficiencies.

Abstract: According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.