Patents by Inventor Sang-Yon Yoon
Sang-Yon Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20140363936Abstract: A thin film transistor (TFT) and an organic light emitting diode (OLED) display device. The TFT and the OLED display device include a substrate, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, a gate electrode insulated from the semiconductor layer, a gate insulating layer insulating the semiconductor layer from the gate electrode, and source and drain electrodes insulated from the gate electrode and partially connected to the semiconductor layer, wherein the semiconductor layer is formed from a polycrystalline silicon layer crystallized by a metal catalyst and the metal catalyst is removed by gettering using an etchant. In addition, the OLED display device includes an insulating layer disposed on the entire surface of the substrate, a first electrode disposed on the insulating layer and electrically connected to one of the source and drain electrodes, an organic layer, and a second electrode.Type: ApplicationFiled: June 12, 2014Publication date: December 11, 2014Inventors: Byoung-Keon Park, Tae-Hoon Yang, Jin-Wook Seo, Ki-Yong Lee, Maxim Lisachenko, Bo-Kyung Choi, Dae-Woo Lee, Kil-Won Lee, Dong-Hyun Lee, Jong-Ryuk Park, Ji-Su Ahn, Young-Dae Kim, Heung-Yeol Na, Min-Jae Jeong, Yun-Mo Chung, Jong-Won Hong, Eu-Gene Kang, Seok-RaK Chang, Jae-Wan Jung, Sang-Yon Yoon
-
Patent number: 8546248Abstract: A method of forming a polycrystalline silicon layer and an atomic layer deposition apparatus used for the same. The method includes forming an amorphous silicon layer on a substrate, exposing the substrate having the amorphous silicon layer to a hydrophilic or hydrophobic gas atmosphere, placing a mask having at least one open and at least one closed portion over the amorphous silicon layer, irradiating UV light toward the amorphous silicon layer and the mask using a UV lamp, depositing a crystallization-inducing metal on the amorphous silicon layer, and annealing the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer. This method and apparatus provide for controlling the seed position and grain size in the formation of a polycrystalline silicon layer.Type: GrantFiled: July 7, 2011Date of Patent: October 1, 2013Assignee: Samsung Display Co., Ltd.Inventors: Yun-Mo Chung, Ki-Yong Lee, Min-Jae Jeong, Jin-Wook Seo, Jong-Won Hong, Heung-Yeol Na, Eu-Gene Kang, Seok-Rak Chang, Tae-Hoon Yang, Ji-Su Ahn, Young-Dae Kim, Byoung-Keon Park, Kil-Won Lee, Dong-Hyun Lee, Sang-Yon Yoon, Jong-Ryuk Park, Bo-Kyung Choi, Maxim Lisachenko
-
Patent number: 8537509Abstract: The present invention relates to a ground fault detecting and controlling method for a parallel-structured high voltage system, and more particularly, such a ground fault detecting and controlling method for a parallel-structured high voltage system, in which it can be more precisely determined whether or not the system operation is emergently stopped based on individual insulation resistance values for respective items of the system, and it can be determined whether there is the possibility of temporary operation of the system in the emergency stop situation of the system operation. According to the present invention, a combined insulation resistance ground fault reference value is calculated based on individual insulation resistance values for respective items of the system, and the entire system is controlled by using the calculated combined insulation resistance ground fault reference value such that a high-accuracy ground fault detecting and controlling method can be provided.Type: GrantFiled: March 29, 2011Date of Patent: September 17, 2013Assignee: Hyundai Motor CompanyInventor: Sang Yon Yoon
-
Publication number: 20120120530Abstract: The present invention relates to a ground fault detecting and controlling method for a parallel-structured high voltage system, and more particularly, such a ground fault detecting and controlling method for a parallel-structured high voltage system, in which it can be more precisely determined whether or not the system operation is emergently stopped based on individual insulation resistance values for respective items of the system, and it can be determined whether there is the possibility of temporary operation of the system in the emergency stop situation of the system operation. According to the present invention, a combined insulation resistance ground fault reference value is calculated based on individual insulation resistance values for respective items of the system, and the entire system is controlled by using the calculated combined insulation resistance ground fault reference value such that a high-accuracy ground fault detecting and controlling method can be provided.Type: ApplicationFiled: March 29, 2011Publication date: May 17, 2012Applicant: HYUNDAI MOTOR COMPANYInventor: Sang Yon Yoon
-
Patent number: 8048783Abstract: A method of forming a polycrystalline silicon layer and an atomic layer deposition apparatus used for the same. The method includes forming an amorphous silicon layer on a substrate, exposing the substrate having the amorphous silicon layer to a hydrophilic or hydrophobic gas atmosphere, placing a mask having at least one open and at least one closed portion over the amorphous silicon layer, irradiating UV light toward the amorphous silicon layer and the mask using a UV lamp, depositing a crystallization-inducing metal on the amorphous silicon layer, and annealing the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer. This method and apparatus provide for controlling the seed position and grain size in the formation of a polycrystalline silicon layer.Type: GrantFiled: February 26, 2010Date of Patent: November 1, 2011Assignee: Samsung Mobile Display Co., Ltd.Inventors: Yun-Mo Chung, Ki-Yong Lee, Min-Jae Jeong, Jin-Wook Seo, Jong-Won Hong, Heung-Yeol Na, Eu-Gene Kang, Seok-Rak Chang, Tae-Hoon Yang, Ji-Su Ahn, Young-Dae Kim, Byoung-Keon Park, Kil-Won Lee, Dong-Hyun Lee, Sang-Yon Yoon, Jong-Ryuk Park, Bo-Kyung Choi, Maxim Lisachenko
-
Publication number: 20110263107Abstract: A method of forming a polycrystalline silicon layer and an atomic layer deposition apparatus used for the same. The method includes forming an amorphous silicon layer on a substrate, exposing the substrate having the amorphous silicon layer to a hydrophilic or hydrophobic gas atmosphere, placing a mask having at least one open and at least one closed portion over the amorphous silicon layer, irradiating UV light toward the amorphous silicon layer and the mask using a UV lamp, depositing a crystallization-inducing metal on the amorphous silicon layer, and annealing the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer. This method and apparatus provide for controlling the seed position and grain size in the formation of a polycrystalline silicon layer.Type: ApplicationFiled: July 7, 2011Publication date: October 27, 2011Applicant: Samsung Mobile Display Co., Ltd.Inventors: Yun-Mo CHUNG, Ki-Yong LEE, Min-Jae JEONG, Jin-Wook SEO, Jong-Won HONG, Heung-Yeol NA, Eu-Gene KANG, Seok-Rak CHANG, Tae-Hoon YANG, Ji-Su AHN, Young-Dae KIM, Byoung-Keon PARK, Kil-Won LEE, Dong-Hyun LEE, Sang-Yon YOON, Jong-Ryuk PARK, Bo-Kyung CHOI, Maxim LISACHENKO
-
Publication number: 20100227443Abstract: A method of forming a polycrystalline silicon layer includes forming an amorphous silicon layer on a substrate by chemical vapor deposition using a gas including a silicon atom and hydrogen gas, and crystallizing the amorphous silicon layer into a polycrystalline silicon layer using a crystallization-inducing metal. The resultant polycrystalline silicon layer has an improved charge mobility.Type: ApplicationFiled: February 26, 2010Publication date: September 9, 2010Applicant: Samsung Mobile Display Co., Ltd.Inventors: Kil-Won LEE, Ki-Yong Lee, Jin-Wook Seo, Tae-Hoon Yang, Byoung-Keon Park, Maxim Lisachenko, Ji-Su Ahn, Young-Dae Kim, Sang-Yon Yoon, Jong-Ryuk Park, Bo-Kyung Choi, Yun-Mo Chung, Min-Jae Jeong, Jong-Won Hong, Heung-Yeol Na, Eu-Gene Kang, Seok-Rak Chang
-
Publication number: 20100227458Abstract: A method of forming a polycrystalline silicon layer and an atomic layer deposition apparatus used for the same. The method includes forming an amorphous silicon layer on a substrate, exposing the substrate having the amorphous silicon layer to a hydrophilic or hydrophobic gas atmosphere, placing a mask having at least one open and at least one closed portion over the amorphous silicon layer, irradiating UV light toward the amorphous silicon layer and the mask using a UV lamp, depositing a crystallization-inducing metal on the amorphous silicon layer, and annealing the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer. This method and apparatus provide for controlling the seed position and grain size in the formation of a polycrystalline silicon layer.Type: ApplicationFiled: February 26, 2010Publication date: September 9, 2010Inventors: Yun-Mo CHUNG, Ki-Yong Lee, Min-Jae Jeong, Jin-Wook Seo, Jong-Won Hong, Heung-Yeol Na, Eu-Gene Kang, Seok-Rak Chang, Tae-Hoon Yang, Ji-Su Ahn, Young-Dae Kim, Byoung-Keon Park, Kil-Won Lee, Dong-Hyun Lee, Sang-Yon Yoon, Jong-Ryuk Park, Bo-Kyung Choi, Maxim Lisachenko
-
Publication number: 20100224883Abstract: A thin film transistor (TFT) and an organic light emitting diode (OLED) display device. The TFT and the OLED display device include a substrate, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, a gate electrode insulated from the semiconductor layer, a gate insulating layer insulating the semiconductor layer from the gate electrode, and source and drain electrodes insulated from the gate electrode and partially connected to the semiconductor layer, wherein the semiconductor layer is formed from a polycrystalline silicon layer crystallized by a metal catalyst and the metal catalyst is removed by gettering using an etchant. In addition, the OLED display device includes an insulating layer disposed on the entire surface of the substrate, a first electrode disposed on the insulating layer and electrically connected to one of the source and drain electrodes, an organic layer, and a second electrode.Type: ApplicationFiled: February 26, 2010Publication date: September 9, 2010Applicant: Samsung Mobile Display Co., Ltd.Inventors: Byoung-Keon PARK, Tae-Hoo Yang, Jin-Wook Seo, Ki-Yong Lee, Maxim Lisachenko, Bo-Kyung Choi, Dae-Woo Lee, Kil-Won Lee, Dong-Hyun Lee, Jong-Ryuk Park, Ji-Su Ahn, Yong-Dae Kim, Heung-Yeol Na, Min-Jae Jeong, Yun-Mo Chung, Jong-Won Hong, Eu-Gene Kang, Seok-Rak Chang, Jae-Wan Jung, Sang-Yon Yoon