Abstract: A gate driving circuit includes: a pull-up control circuit configured to control a voltage of a pull-up control node in response to a pull-up control signal; a pull-down control circuit configured to control a voltage of a pull-down control node in response to the voltage of the pull-up control node; a carry output circuit configured to output a carry signal in response to the voltage of the pull-up control node and the voltage of the pull-down control node; and a gate output circuit configured to output a plurality of gate signals having different timings in response to the voltage of the pull-up control node and the voltage of the pull-down control node, wherein a width of the carry signal is greater than a width of each of the gate signals.

Abstract: A light emitting display device includes: a substrate; a driving element layer on the substrate and including a transistor and a planarization film covering the transistor; a second electrode on the planarization film and including a contact opening; a separator on the planarization film and has a reverse-tapered sidewall; a pixel defining layer including a first opening exposing a portion of the second electrode, a second opening exposing a portion of the separator, and a third opening corresponding to the contact opening of the second electrode; and a first electrode on the pixel defining layer, wherein the first electrode is electrically connected to the transistor of the driving element layer through the contact opening of the second electrode and the third opening of the pixel defining layer.

Abstract: An embodiment provides a display device including a pixel circuit layer including a base layer and a pixel circuit; and a light emitting element disposed on the pixel circuit layer and including a first electrode, a second electrode, and a light emitting layer electrically connected the first electrode and the second electrode. The pixel circuit includes a first transistor. The first transistor includes a first gate electrode, a first active layer, a first source electrode, and a first drain electrode. The first electrode forms an open area. The first gate electrode and the open area overlap each other in a plan view.

Abstract: A display device includes a first vertical power line extending in a first direction and receiving a first power source; and a first horizontal power line extending in a second direction intersecting the first direction between a first pixel and a second pixel and receiving the first power source, each of the first pixel and the second pixel includes first to third sub-pixels sequentially disposed in the first direction, the first pixel includes a first common pattern between the first sub-pixel and the second sub-pixel extending in the second direction, the first sub-pixel of the first pixel and the second sub-pixel of the first pixel share the first common pattern and are connected to the first vertical power line, and the third sub-pixel of the first pixel shares the first horizontal power line with the first sub-pixel of the second pixel.

Abstract: A scan signal driver includes: a plurality of stages configured to be driven by dividing a first frame period into a display period and a sensing period, and to sequentially output scan signals at the display period, wherein each of the plurality of stages comprises: an output control circuit; and a memory control circuit, wherein the scan driver is configured to: irregularly set a specific stage of the plurality of stages at a display period every frame; control the specific stage to: store a voltage by using the memory control circuit; and output a sensing signal by using the stored voltage at a sensing period, and the memory control circuit includes: a second memory transistor configured to electrically connect an M node with an I node; and a third memory transistor configured to electrically connect the output control circuit with the I node.

Abstract: A scan signal driver includes: a plurality of stages configured to be driven by dividing a first frame period into a display period and a sensing period, and to sequentially output scan signals at the display period, wherein each of the plurality of stages comprises: an output control circuit; and a memory control circuit, wherein the scan driver is configured to: irregularly set a specific stage of the plurality of stages at a display period every frame; control the specific stage to: store a voltage by using the memory control circuit; and output a sensing signal by using the stored voltage at a sensing period, and the memory control circuit includes: a second memory transistor configured to electrically connect an M node with an I node; and a third memory transistor configured to electrically connect the output control circuit with the I node.

Abstract: A display device includes a pixel circuit on a substrate and including a transistor, a first pixel electrode on the pixel circuit and electrically connected to the pixel circuit, a bank on the first pixel electrode and including first, second, third, and fourth open parts, a first contact electrode on the bank and the first and second open parts and in contact with the first pixel electrode through the first open part, a second pixel electrode overlapping the second and third open parts, the second pixel electrode and the first pixel electrode formed as a same layer, a second contact electrode on the bank and the third and fourth open parts and in contact with the second pixel electrode through the third open part, and a common pixel electrode overlapping the fourth open part, the common pixel electrode and the second pixel electrode formed as a same layer.

Abstract: A display device includes a substrate, a first semiconductor layer, and including first and second transistors, first and second gate conductive layers above the first semiconductor layer, a second semiconductor layer above the second gate conductive layer, and including a third transistor, a third gate conductive layer above the second semiconductor layer, an insulating film defining a valley surrounding the first semiconductor layer, the first gate conductive layer, the second gate conductive layer, the second semiconductor layer, and the third gate conductive layer, a connection metal conductive layer above the insulating film, and including a first connection electrode electrically connecting the first and third transistors, the first connection electrode including a (1-1)-th region overlapping the first transistor, and a (1-2)-th region and a (1-3)-th region overlapping the third transistor and connected to the third transistor, and first and second data conductive layers above the connection metal condu

Abstract: A gate driving circuit includes: a pull-up control circuit configured to control a voltage of a pull-up control node in response to a pull-up control signal; a pull-down control circuit configured to control a voltage of a pull-down control node in response to the voltage of the pull-up control node; a carry output circuit configured to output a carry signal in response to the voltage of the pull-up control node and the voltage of the pull-down control node; and a gate output circuit configured to output a plurality of gate signals having different timings in response to the voltage of the pull-up control node and the voltage of the pull-down control node, wherein a width of the carry signal is greater than a width of each of the gate signals.

Abstract: Provided herein may be a pixel. The pixel may include a driving transistor including a gate electrode coupled to a first node, a first electrode coupled to a first power line, and a second electrode coupled to a second node, a control transistor including a gate electrode coupled to the first node, a first electrode coupled to the second node, and a second electrode that is different from the first electrode, a first emission unit including at least one light-emitting element coupled between the second electrode of the control transistor and a second power line, and a second emission unit including at least one light-emitting element coupled between the second node and the second power line, wherein the second electrode of the control transistor is coupled to a first electrode of the first emission unit.

Abstract: A display substrate has first and second conductive layers separated from one another by an insulation layer. The first and second conductive layers are used to integrally form on the display substrate, pixel units in a relatively central display area of the substrate and integrated gate driving circuitry as well as associated wirings thereof in one or more peripheral areas. The first and second conductive layers are covered by a first protection layer made of a first electrically insulative material. A second and supplementing protection layer is provided on top of the first protection layer. The supplementing protection layer (buffer layer) is formed of a material different from that of the first protection layer so as to provide supplemental resistance against corrosive chemical agents and supplemental resistance against formation of cracks.

Abstract: A display device includes a bank layer including a first bank portion and a second bank portion, the first bank portion includes a (1-1) bank portion and at least one (1-2) bank portion having an average height less than the (1-1) bank portion, the second bank portion includes a (2-1) bank portion, at least one (2-2) bank portion and having an average height less than the (2-1) bank portion, and at least one (2-3) bank portion with the (2-2) bank portion therebetween and having an average height less than the (2-2) bank portion, the (1-1) bank portion exposes an upper end of a side surface of the (1-2) bank portion, the (2-1) bank portion exposes an upper end of a side surface of the (2-2) bank portion, and the (2-2) bank portion exposes an upper end of a side surface of the (2-3) bank portion.

Abstract: A display device may include: a substrate including a display area having first to third areas, and a non-display area; first pixels in the first area, second pixels in the second area, and third pixels in the third area; a pad part located in the non-display area, and electrically connected to the first to third pixels; a line part including a first line between the pad part and the first area, a second line between the pad part and the second area, and a third line between the pad part and the second area; a bridge line extending in a first direction, and located in the second and third areas; and an extension line extending in a second direction, and located in the second area and electrically connected with the bridge line. The extension line may be electrically connected with the third line.

Abstract: Provided is a tiled display. The tiled display includes: a first display device including a first display area including pixels, a second display device including a second display area including pixels adjacent to the first display area, and a seam between the first display area and the second display area. Each of the first display device and the second display device includes: a first base part supporting a respective one of the first display device and the second display device, a thin-film transistor layer on the first base part, the thin-film transistor layer including thin-film transistors included in the pixels and including connection lines in the seam, and bridge electrodes in the seam to couple between the connection lines of the first display device and the second display device.

Abstract: A display device includes a base layer including a display area and a non-display area, an emission unit including a first electrode electrically connected to a first driving power source, a second electrode electrically connected to a second driving power source, and a light-emitting element disposed between first and second electrodes, a first transistor including a first terminal electrically connected to the first driving power source, a second terminal electrically connected to the first electrode of the emission unit, and a gate electrode electrically connected to a first node, a second transistor including a first terminal electrically connected to a data line, a second terminal electrically connected to the first node, and a gate electrode electrically connected to a scan line, and an electrostatic discharge circuit disposed in the display area and disposed between the first driving power source and the data line.

Abstract: A display device, includes: pixels at a display area; gate lines at the display area, and connected to the pixels; carry clock lines and scan clock lines at the display area; and a gate driving circuit distributedly located at the display area, and connected to the carry clock lines, the scan clock lines, and the gate lines. The gate driving circuit includes a plurality of stages, each of the stages to output, as a carry signal, a carry clock signal supplied through a corresponding carry clock line from among the carry clock lines, and to output, as a scan signal, a scan clock signal supplied through a corresponding scan clock line from among the scan clock lines. The corresponding carry clock line and the corresponding scan clock line corresponding to one stage from among the stages are spaced from each other with at least one of the pixels interposed therebetween.

Abstract: A display device includes: a display area and a non-display area; a first pixel area and a second pixel area, each provided in the display area; scan lines extending in a first direction and disposed in the first pixel area and the second pixel area; first sub-scan lines extending in a second direction and disposed in the first pixel area, the second direction intersecting the first direction; second sub-scan lines extending in the second direction and disposed in the first pixel area and the second pixel area; and a pad part provided in the non-display area, the pad part being electrically connected to the first sub-scan lines and the second sub-scan lines. The scan lines are electrically connected to at least one of the first sub-scan lines and the second sub-scan lines. The first sub-scan lines do not overlap the second pixel area in a plan view.

Abstract: A scan driver includes active stages. Each active stage includes a first transistor that resets a control node, a second transistor that transfers a previous carry signal to the control node, a third transistor that transfers a scan clock signal to a scan output node, a first capacitor electrically connected between the control node and the scan output node, a fourth transistor that transfers a first low voltage to the scan output node, a fifth transistor that transfers a carry clock signal to a carry output node, a sixth transistor that electrically connects the control node to the carry output node, and a seventh transistor that transfers a second low voltage to the control node.

Abstract: A scan driver includes active stages. Each active stage includes a first transistor that resets a control node, a second transistor that transfers a previous carry signal to the control node, a third transistor that transfers a scan clock signal to a scan output node, a first capacitor electrically connected between the control node and the scan output node, a fourth transistor that transfers a first low voltage to the scan output node, a fifth transistor that transfers a carry clock signal to a carry output node, a sixth transistor that electrically connects the control node to the carry output node, and a seventh transistor that transfers a second low voltage to the control node.

Abstract: A display device includes a data driver that outputs a first data signal and a second data signal of different voltages, and a pixel that emits light in response to the first data signal and the second data signal. The pixel includes a current generator generating a driving current corresponding to the first data signal, a first light emitting part including a first electrode, a second electrode, and a first light emitting element, a second light emitting part including a third electrode, a fourth electrode connected, and a second light emitting element, and a current controller controlling a divided current supplied to the second light emitting part in response to the second data signal.