Patents by Inventor Sang-Youl Kwon

Sang-Youl Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Flash memory devices with selective bit line discharge paths and methods of operating the same
    Patent number: 8363482
    Abstract: Provided is a flash memory device that can include a memory cell configured to store data, a local bit line that is connected to the memory cell, a global bit line that is connected to the local bit line, a discharge transistor that is connected to the global bit line, and that is configured to selectively connect the global bit line to a reference level responsive to a discharge control signal, and a discharge control circuit, that is connected to the discharge transistor via the discharge control signal, and that is configured to selectively disable the discharge transistor during an erase interval occurring before a verify interval of an erase verification operation carried out by the flash memory device.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: January 29, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Euido Kim, BongYong Lee, Haebum Lee, Sang-Youl Kwon, Jin-Young Kim, Hye Yeon Yun, Houng-kuk Jang
  • FLASH MEMORY DEVICES WITH SELECTIVE BIT LINE DISCHARGE PATHS AND METHODS OF OPERATING THE SAME
    Publication number: 20110216602
    Abstract: Provided is a flash memory device that can include a memory cell configured to store data, a local bit line that is connected to the memory cell, a global bit line that is connected to the local bit line, a discharge transistor that is connected to the global bit line, and that is configured to selectively connect the global bit line to a reference level responsive to a discharge control signal, and a discharge control circuit, that is connected to the discharge transistor via the discharge control signal, and that is configured to selectively disable the discharge transistor during an erase interval occurring before a verify interval of an erase verification operation carried out by the flash memory device.
    Type: Application
    Filed: June 10, 2010
    Publication date: September 8, 2011
    Inventors: Euido Kim, Bong Yong Lee, Haebum Lee, Sang-Youl Kwon, Jin-Young Kim, Hye Yeon Yun, Houng-kuk Jang
  • Semiconductor memory device and method for repairing the same
    Patent number: 7876632
    Abstract: A semiconductor memory device includes a main cell array region, a first redundancy cell array region and a first dummy cell array region that are formed at one side of the main cell array region, and a second redundancy cell array region and a second dummy cell array region that are formed at the other side of the main cell array region. The first redundancy cell array region includes a first redundancy bitline, and the first dummy cell array region includes first dummy bitlines. The second redundancy cell array region includes a second redundancy bitline, and the second dummy cell array region includes second dummy bitlines. The first and second redundancy cell array regions are disposed closer to the main cell array region than the first and second dummy cell array regions.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: January 25, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-Yong Lee, Heon-Kyu Lee, Kwang-Soo Kim, Sang-Youl Kwon
  • Semiconductor memory device and method for repairing the same
    Publication number: 20080137454
    Abstract: A semiconductor memory device includes a main cell array region, a first redundancy cell array region and a first dummy cell array region that are formed at one side of the main cell array region, and a second redundancy cell array region and a second dummy cell array region that are formed at the other side of the main cell array region. The first redundancy cell array region includes a first redundancy bitline, and the first dummy cell array region includes first dummy bitlines. The second redundancy cell array region includes a second redundancy bitline, and the second dummy cell array region includes second dummy bitlines. The first and second redundancy cell array regions are disposed closer to the main cell array region than the first and second dummy cell array regions.
    Type: Application
    Filed: December 11, 2007
    Publication date: June 12, 2008
    Inventors: Bong-Yong Lee, Heon-Kyu Lee, Kwang-Soo Kim, Sang-Youl Kwon