Abstract: Provided are a compound represented by Formula 24, an organic electric element comprising a first electrode, a second electrode, and an organic material layer formed between the first electrode and the second electrode and comprising the compound of Formula 24, and an electronic device thereof, the element and device having improved driving voltage, luminous efficiency and lifetime from the employment of the compound.

Abstract: A micro-lens array is provided. The micro-lens array includes a transparent substrate, a plurality of polarizers disposed on the transparent substrate, a passivation layer covering the plurality of polarizers, and a plurality of micro-lenses disposed on the passivation layer, wherein light reflected to an object passes through the transparent substrate, and then, is polarized based on a plurality of different polarization orientations formed by the plurality of polarizers and is incident on the plurality of micro-lenses.

Abstract: The present disclosure relates to a high energy density lithium secondary battery having significantly improved high-temperature storage characteristics and lifespan characteristics, which are problematic when a silicon-based negative electrode active material is applied. Specifically, a lithium secondary battery according to an exemplary embodiment includes a positive electrode; a negative electrode facing the positive electrode and including a silicon-based negative electrode active material; and a non-aqueous electrolyte containing a non-aqueous organic solvent including a di-fluoro-based organic solvent and a lithium salt, wherein a content of the di-fluoro-based organic solvent is 5 to 20 vol % with respect to a total volume of the non-aqueous organic solvent.

Abstract: An inkjet resin composition includes about 20% to about 30% by weight of 2-ethylhexyl acrylate, about 20% to about 30% by weight of 4-hydroxybutyl acrylate, about 40% to about 50% by weight of isodecyl acrylate, about 1% to about 10% by weight of urethane acrylate, about 1% to about 5% by weight of an initiator, about 1% to about 5% by weight of a silane coupling agent, and about 0.05% to about 1% by weight of a surface flow control additive.

Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

Abstract: The present inventive concept relates to a substrate processing apparatus comprising: a chamber; a substrate support part which supports at least one substrate in the chamber; a lower plate which is disposed above the substrate support part; and an upper plate which is disposed above the lower plate, wherein: the upper plate includes a first spray hole which provides a first gas and a second spray hole which provides a second gas; and the lower plate includes a first opening which is disposed under the first spray hole so as to allow the first gas provided from the first spray hole to pass therethrough and a second opening which is disposed under the second spray hole so as to allow the second gas provided from the second spray hole to pass therethrough.

Abstract: In one example, a semiconductor device includes a first substrate with a first substrate top side, a first substrate bottom side opposite to the first substrate top side, a first substrate lateral side interposed between the first substrate top side and the first substrate bottom side, and a first substrate conductive structure. An electronic component is coupled to the first substrate top side and coupled to the first substrate conductive structure. A support includes a support wall having a first ledge coupled to the first substrate top side, a first riser coupled to the first substrate lateral side, and a second ledge extending from the first riser away from the first substrate lateral side. Other examples and related methods are also disclosed herein.

Abstract: A solar panel disassembling apparatus according to an embodiment of the present disclosure separates a glass plate of a solar panel and a film layer bonded to the glass plate from each other. The solar panel disassembling apparatus includes a supply module that stands and fixes the solar panel such that a bond line between the glass plate and the film layer is exposed upward and downward and that moves the solar panel in a parallel direction parallel to a bonding surface between the glass plate and the film layer, and a wire-shaped cutting blade that is disposed in front of the solar panel in a movement direction of the solar panel to have a distance from the supply module, is disposed in parallel to the bonding surface, and separates the glass plate and the film layer from each other.

Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

Abstract: Provided is an image display system displaying an image obtained from an image capturing device. A method of operating a terminal in the image display system includes displaying a first user interface (UI) screen including the image through a display, obtaining a first user input indicating a pointing position in the image, generating a first enlarged image of an enlargement target area corresponding to the pointing position, in response to the first user input, and displaying a second UI screen including the first enlarged image through the display, wherein an input time of the first user input is greater than or equal to a preset threshold time.

Abstract: An apparatus for preparing lithium sulfide includes a reaction chamber that has a reaction space for generating lithium sulfide and is provided to move a supplied lithium raw material in a predetermined direction; a lithium raw material supply unit provided to continuously supply the lithium raw material to an upstream side of the reaction chamber in the predetermined direction; a hydrogen sulfide supply unit provided to supply hydrogen sulfide to the reaction chamber; a heating unit; a lithium sulfide recovery unit provided on a downstream side of the reaction chamber in the predetermined direction and provided to recover lithium sulfide that is generated by a reaction between the hydrogen sulfide and the lithium raw material in the reaction chamber; an inert gas supply unit provided to supply an inert gas to the upstream side of the reaction chamber in the predetermined direction; and a moisture removal unit.

Abstract: A crime type inference system based on text data, may include: a keywords dictionary construction unit configured to receive crime source data, and generate a crime type keywords dictionary by extracting crime keywords; a data set construction unit configured to generate a dataset for crime type learning by using the crime source data and the keywords dictionary; a crime type prediction model training unit configured to generate a crime type prediction model by using the dataset, and train the crime type prediction model; and a crime type inference unit configured to infer a crime type by using new crime data.

Abstract: Provided is a surveillance planning device configured to generate a checklist with respect to a region based on spatial information and object information of the region, obtain device installation condition information based on a user response to the checklist, and recommend, to a user, a list of devices to be installed in the region and an installation location of the devices based on the spatial information, the object information, and the device installation condition information.

Abstract: A printed circuit board includes a first insulating layer having a through cavity and containing an insulating material. A length between one side surface and the other side surface opposite to the one side surface of the through cavity is greater than a thickness of the first insulating layer, and the first insulating layer includes a recess located in each of an upper edge and a lower edge of the one side surface of the through cavity.

Abstract: An apparatus for providing temperature information includes a receiver configured to receive a first image and a second image of a same scene, the first image being captured by a visible light camera and the second image being captured by an infrared camera, an image editing device configured to set a reference area for an object selected by a user based on pixel values in the second image and generate an edited image with the reference area displayed in the first image or the second image, and a transmitter configured to transmit the edited image.

Abstract: Disclosed are novel structures and methods for 3D NVM built with vertical transistors above a logic layer. A first embodiment has a conductive film under the transistors and serving as a common node in a memory block. The conductive film may be from a semiconductor layer used to build the transistors. Metal lines are disposed above the transistors for connection through 3D vias to underlying circuitry. Contact plugs may be formed between transistors and metal lines. The conductive film may be coupled to underlying circuitry through contacts on the conductive film or through interconnect vias underneath the film. A second embodiment has conductive lines disposed under the transistors. Either of conductive lines and metal lines may serve as source lines and the other as bit lines for the memory. For low parasitic resistances, the conductive lines may be shorted to bypass metal lines residing in underlying logic layer.

Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.