Abstract: A printed circuit board includes a first insulating layer having a through cavity and containing an insulating material. A length between one side surface and the other side surface opposite to the one side surface of the through cavity is greater than a thickness of the first insulating layer, and the first insulating layer includes a recess located in each of an upper edge and a lower edge of the one side surface of the through cavity.

Abstract: An apparatus for providing temperature information includes a receiver configured to receive a first image and a second image of a same scene, the first image being captured by a visible light camera and the second image being captured by an infrared camera, an image editing device configured to set a reference area for an object selected by a user based on pixel values in the second image and generate an edited image with the reference area displayed in the first image or the second image, and a transmitter configured to transmit the edited image.

Abstract: Disclosed are novel structures and methods for 3D NVM built with vertical transistors above a logic layer. A first embodiment has a conductive film under the transistors and serving as a common node in a memory block. The conductive film may be from a semiconductor layer used to build the transistors. Metal lines are disposed above the transistors for connection through 3D vias to underlying circuitry. Contact plugs may be formed between transistors and metal lines. The conductive film may be coupled to underlying circuitry through contacts on the conductive film or through interconnect vias underneath the film. A second embodiment has conductive lines disposed under the transistors. Either of conductive lines and metal lines may serve as source lines and the other as bit lines for the memory. For low parasitic resistances, the conductive lines may be shorted to bypass metal lines residing in underlying logic layer.

Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

Abstract: The present disclosure relates to an expanded foam solution for forming a thermosetting expanded foam having excellent flame retardancy produced using the same. According to the present disclosure, nanoclay is mixed with a polyol-based compound using ultrasonic waves, an isocyanate-based compound is added, and a trimerization catalyst or an isocyanurate compound is mixed with the polyol-based compound so that an isocyanurate structure is formed.

Abstract: Disclosed herein is a mobile cleaning device with a sterilization function.

Abstract: Disclosed are novel structures and methods for 3D NVM built with vertical transistors above a logic layer. A first embodiment has a conductive film under the transistors and serving as a common node in a memory block. The conductive film may be from a semiconductor layer used to build the transistors. Metal lines are disposed above the transistors for connection through 3D vias to underlying circuitry. Contact plugs may be formed between transistors and metal lines. The conductive film may be coupled to underlying circuitry through contacts on the conductive film or through interconnect vias underneath the film. A second embodiment has conductive lines disposed under the transistors. Either of conductive lines and metal lines may serve as source lines and the other as bit lines for the memory. For low parasitic resistances, the conductive lines may be shorted to bypass metal lines residing in underlying logic layer.

Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

Abstract: Disclosed is a toilet bowl bidet capable of preventing droplets from splashing, the toilet bowl bidet including a washing water supply hose (150) having an air pump (180) disposed at an outlet side of a washing water valve (160) and configured to mix air into washing water supplied to a bidet nozzle unit (140), wherein the bidet nozzle unit (140) includes first and second washing water passages (141) and (143) respectively including bidet nozzles (142) and (144), a third washing water passage (145) including a shield nozzle (146), and a distributor 148 configured to guide the washing water to a selected one of the first, second, and third washing water passages (141), (143), and (145). A controller (170) is configured to, when a flushing operation is performed, control the distributor (148) to supply air-mixed washing water to the third washing water passage (145) and open the washing water valve (160).

Abstract: The present disclosure relates to an expanded foam solution for forming a thermosetting expanded foam having excellent flame retardancy produced using the same. According to the present disclosure, nanoclay is mixed with a polyol-based compound using ultrasonic waves, an isocyanate-based compound is added, and a trimerization catalyst or an isocyanurate compound is mixed with the polyol-based compound so that an isocyanurate structure is formed.

Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

Abstract: Provided is an image display system displaying an image obtained from an image capturing device. A method of operating a terminal in the image display system includes displaying a first user interface (UI) screen including the image through a display, obtaining a first user input indicating a pointing position in the image, generating a first enlarged image of an enlargement target area corresponding to the pointing position, in response to the first user input, and displaying a second UI screen including the first enlarged image through the display, wherein an input time of the first user input is greater than or equal to a preset threshold time.

Abstract: A printed circuit board includes a first insulating layer having a through cavity and containing an insulating material. A length between one side surface and the other side surface opposite to the one side surface of the through cavity is greater than a thickness of the first insulating layer, and the first insulating layer includes a recess located in each of an upper edge and a lower edge of the one side surface of the through cavity.

Abstract: Disclosed are novel structures and methods for 3D CMOS integrated circuits built with vertical transistors. A gate extension is selectively patterned by first patterning a sacrificial dielectric disposed on a gate material. A 3D CMOS IC comprises vertical transistors of one type constructed in one level and those of an opposite type in another level. The gate of lower-level vertical transistors may be coupled to a top interconnect directly through a 3D gate contact or indirectly through an upper-level via and a lower-level contact. A common-gate coupling may be formed between vertical transistors in different levels through a strapping contact or a gate via. A common-drain coupling may be formed between vertical transistors in different levels by forming upper-level vertical transistor on a piece of conductive film disposed over lower-level vertical transistor with or without an intervening top contact for lower-level vertical transistor.

Abstract: Disclosed are novel structures and methods for 3D CMOS integrated circuits built with vertical transistors. A gate extension is selectively patterned by first patterning a sacrificial dielectric disposed on a gate material. A 3D CMOS IC comprises vertical transistors of one type constructed in one level and those of an opposite type in another level. The gate of lower-level vertical transistors may be coupled to a top interconnect directly through a 3D gate contact or indirectly through an upper-level via and a lower-level contact. A common-gate coupling may be formed between vertical transistors in different levels through a strapping contact or a gate via. A common-drain coupling may be formed between vertical transistors in different levels by forming upper-level vertical transistor on a piece of conductive film disposed over lower-level vertical transistor with or without an intervening top contact for lower-level vertical transistor.

Abstract: Structures for 3D sense amplifiers for 3D memories are disclosed. A first embodiment uses one type of vertical transistors in constructing 3D sense amplifiers. A second embodiment uses both n- and p-type transistors for 3D sense amplifiers. Either or both of n- and p-type transistors are vertical transistors. The n- and p-type transistors may reside on different levels, or on the same level above a substrate if both are vertical transistors. In any embodiment, different options are available for gate contact formation. In any embodiments and options or alternatives thereof, one or more sense-enable circuits may be used. Sense amplifiers for several bit lines may be staggered on one or both sides of a memory array. Column multiplexers may be used to couple particular bit lines to data outputs. Bit-line multiplexers may be used to couple certain bit lines to shared 3D sense amplifiers.

Abstract: Proposed are an organic-inorganic composite synthetic resin using a highly flame-retardant organically modified nanoparticle, and a production method thereof. The method for producing the organic-inorganic composite synthetic resin using a highly flame-retardant organically modified nanoparticle includes the steps of: adding and stirring metal ion-based phosphinate, melamine cyanurate, and nanoclay to a container containing an aqueous or oily solvent, applying ultrasonic waves and high pressure energy to the stirred solution to prepare a highly flame-retardant organically modified silicate solution through a chemical bonding, and then adding a synthetic resin to form synthetic leather and foam used as life consumer goods to the silicate solution, processing and drying it.

Abstract: Proposed are an organic-inorganic composite synthetic resin using a highly flame-retardant organically modified nanoparticle, and a production method thereof. The method for producing the organic-inorganic composite synthetic resin using a highly flame-retardant organically modified nanoparticle a includes the steps of: adding and stirring metal ion-based phosphinate, melamine cyanurate, and nanoclay to a container containing an aqueous or oily solvent, applying ultrasonic waves and high pressure energy to the stirred solution to prepare a highly flame-retardant organically modified silicate solution through a chemical bonding, and then adding a synthetic resin to form synthetic leather and foam used as life consumer goods to the silicate solution, processing and drying it.

Abstract: This specification discloses a quantum public-key cryptosystem. The quantum public-key cryptosystem may use two rotation operators R{circumflex over (n)}(?) and R{circumflex over (m)}(?) satisfying a cyclic evolution. The two rotation operators R{circumflex over (n)}(?) and R{circumflex over (m)}(?) do not have a commutation relation or an anti-commutation relation with each other. The commutation relation or the anti-commutation relation is established when either of the following conditions is satisfied: ?=2i?, ?=2j?, or {circumflex over (n)}·{circumflex over (m)}=1 (i, j=integer), and ?=(2k+1)?, ?=(2l+1)?, or {circumflex over (n)}·{circumflex over (m)}=0 (k, l=integer).