Abstract: A display apparatus includes a light-emitting panel including a first substrate and a plurality of light-emitting devices disposed on the first substrate, and a color panel including a second substrate, a bank disposed on a lower surface of the second substrate in a direction to the first substrate and including a plurality of first openings each corresponding to emission areas of the plurality of light-emitting devices, a functional layer arranged in the plurality of first openings, a first protrusion pattern disposed on the bank, and a second protrusion pattern disposed on the bank. The first protrusion pattern is arranged between adjacent ones of the plurality of first openings, and the second protrusion pattern is spaced apart from the first protrusion pattern.

Abstract: A semiconductor fabrication apparatus comprising a light source configured to emit light, a substrate stage arranged to receive a substrate exposed to the emitted light, a reticle arranged between the substrate stage and the light source, and a reticle stage arranged to receive the reticle. The reticle stage including a lower plate, an upper plate arranged above the lower plate, an actuator connected to the lower plate configured to move in a direction parallel to the upper plate, a first cable slab arranged between the upper plate and the lower plate and connected to one side of the actuator, and a first cable cover that surrounds an outer periphery of the first cable slab and contacts the lower plate when the first cable slab becomes bent.

Abstract: All embodiments of the present invention basically include an upper transistor and a lower transistor connected in series between a power supply and ground. The upper transistor and the lower transistor have a shared source (or drain) terminal which becomes a single bidirectional node. They further comprise a sensing gate and a logic gate. The sensing inverter has a function of sensing a voltage at the single bidirectional node and comparing it with an input transition voltage since an input terminal of the sensing inverter is connected to the single bidirectional node. An initial voltage at the single bidirectional node of the filter-based lock-in circuit is almost the same as the input transition voltage of the sensing inverter, where the input transition voltage is an input voltage which causes an output voltage to be V DD 2 .

Abstract: All embodiments of the present invention basically include an upper transistor and a lower transistor connected in series between a power supply and ground. The upper transistor and the lower transistor have a shared source (or drain) terminal which becomes a single bidirectional node. They further comprise a sensing gate and a logic gate. The sensing inverter has a function of sensing a voltage at the single bidirectional node and comparing it with an input transition voltage since an input terminal of the sensing inverter is connected to the single bidirectional node. An initial voltage at the single bidirectional node of the filter-based lock-in circuit is almost the same as the input transition voltage of the sensing inverter, where the input transition voltage is an input voltage which causes an output voltage to be VDD/2.

Abstract: The pin number reduction circuit circuits and methodology of the present invention provide a higher pseudo power supply and a lower pseudo power supply for a digital functional section in mixed-signal IC, memory IC, and SOC including analog functional section and digital (or memory) functional section in order to reduce digital noise coupling. The circuit and methodology of the present invention basically includes resistors, capacitors, transistors, and amplifiers. It is noted that analog functional section is coupled between a positive power supply and a negative power supply, which are connected to two pins. One amplifier with a PMOS transistor and one resistor string provides a higher pseudo power supply, and the other amplifier with an NMOS transistor and the other resistor string provides a lower pseudo power supply so that a digital functional section is coupled between these pseudo power supplies.

Abstract: The pin number reduction circuit circuits and methodology of the present invention provide a higher pseudo power supply and a lower pseudo power supply for a digital functional section in mixed-signal IC, memory IC, and SOC including analog functional section and digital (or memory) functional section in order to reduce digital noise coupling. The circuit and methodology of the present invention basically includes resistors, capacitors, transistors, and amplifiers. It is noted that analog functional section is coupled between a positive power supply and a negative power supply, which are connected to two pins. One amplifier with a PMOS transistor and one resistor string provides a higher pseudo power supply, and the other amplifier with an NMOS transistor and the other resistor string provides a lower pseudo power supply so that a digital functional section is coupled between these pseudo power supplies.

Abstract: Two cost-effective low-voltage drop reference generation circuits for A/D converter of the present invention generates a plurality of reference voltages characterized by voltage increments between two fixed reference voltages, which are able to be close to positive rail and negative rail (or ground). These low-voltage drop generation circuits not only greatly increases the total reference voltage range (i.e., increases voltage difference between the most positive reference voltage and the most negative reference voltage, increases VREFT?VREFB, maximizes the most positive reference voltage and minimizes the most negative reference voltage), but also enables A/D converter to convert rail-to-rail analog input with maintaining good power supply rejection with respect to positive power and negative power (or ground).

Abstract: The smart start-up circuits basically include a sensor, two stacked PMOS transistors, two stacked NMOS transistors, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensor, the output voltage of the sensor turns on the corresponding transistor, which provides a current to its output until the voltage at feedback reaches the midpoint voltage. The time to reach the midpoint voltage at a load is simply equal to the charge stored at the load divided by the current, which can be scaled by a device aspect ratio of the transistor. Consequently, all smart start-up circuits provide an initial output voltage level closer to the output voltage level that reaches the equilibrium according to schedule.

Abstract: The smart charge-pump circuits basically include a high-performance charge-pump circuit as well as a smart lock-in circuit. After the smart charge-pump circuit sensors an initial condition and responds accordingly, it will begin to operate fully as a high performance charge-pump.

Abstract: Two reference generation circuits for D/A converter of the present invention generates a plurality of reference voltages characterized by voltage increments between two fixed reference voltages. These generated reference voltages greatly reduces unbalanced charge-injection errors that any fully differential architecture can not remove. The inaccuracy of D/A converters caused by the corrupted reference voltages is greatly minimized.

Abstract: The variable lock-in circuits basically include a sensor, triggering transistors, current mirror, current source, an N-bit triggering circuit array, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensor, the output voltage of the sensor turns on the triggering transistors, which provide a total current to its output through the current mirror until the voltage at feedback reaches the midpoint voltage. The time to reach the midpoint voltage at a filter is simply equal to the charge stored at the filter divided by the total current, which is controlled by an N-bit digital input and a device aspect ratio of each triggering transistor. Consequently, all variable lock-in circuits provide an initial loop condition closer to the expected loop condition according to schedule.

Abstract: Two reference generation circuits for A/D converter of the present invention generates a plurality of reference voltages characterized by voltage increments between two fixed reference voltages. These generated reference voltages greatly reduces unbalanced charge injection errors that any fully differential architecture can not remove. The inaccuracy of A/D converters caused by the corrupted reference voltages is greatly minimized.

Abstract: The adjustable lock-in circuits basically include a sensor, a reference voltage, two stacked PMOS transistors, two stacked NMOS transistors, and a feedback line. The sensor compares a feedback voltage with a reference voltage. If the sensing voltage does not reach the reference voltage, the output voltage of the sensor turns on the corresponding transistor, which provides a current to its output until the voltage at feedback reaches the reference voltage. The time to reach the expected voltage level is simply equal to the charge stored at the filter divided by the current, which can be scaled by a device aspect ratio of the transistor. Consequently, all adjustable lock-in circuits provide an adjustable initial loop condition closer to the expected loop condition according to a targeted lock-in time. In addition, the initial loop condition is varied by changing the reference voltage level.

Abstract: The smart lock-in circuits basically include a sensor, two stacked PMOS transistors, two stacked NMOS transistors, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensor, the output voltage of the sensor turns on the corresponding transistor, which provides a current to its output until the voltage at feedback reaches the midpoint voltage. The time to reach the midpoint voltage at a filter is simply equal to the charge stored at the filter divided by the current, which can be scaled by a device aspect ratio of the transistor. Consequently, all smart lock-in circuits provide an initial loop condition closer to the expected loop condition according to schedule.

Abstract: The four types of the controllable idle time current mirror circuits are presented with an improvement in productivity, performance, cost, chip area, power consumption, and design time. The controllable idle time current mirror circuits basically include a sensing block, triggering transistors, current mirror, current source, a n-bit control circuit array, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensing gate, the triggering transistors provide a current to its output through the current mirror until the voltage at feedback reaches the midpoint voltage. Time to reach the midpoint voltage at a load is simply equal to the charge stored at the load divided by the total current, which is controlled by an N-bit digital input and a device aspect ratio of each triggering transistor.

Abstract: The smart charge-pump circuits basically include a high-performance charge-pump circuit as well as a smart lock-in circuit. After the smart charge-pump circuit sensors an initial condition and responds accordingly, it will begin to operate fully as a high performance charge-pump.

Abstract: One of the high-performance charge-pump circuits basically includes two switch mirror circuits, two current sources, two switches, and an inverter. In the switch mirror, the switch coupled to the diode-connected reference transistor is indirectly mirrored to the output. The great advantage is to utilize the switch mirrors as a part of building cascodes at the output. Consequently, all high-performance charge-pump circuits suppress any charge-injection errors, reduce charge-pump offset, increase the output impedance for effective current injection, and reduce chare-sharing problem.

Abstract: The four types of the Z-state circuits basically include a sensing gate, two stacked PMOS transistors, and a feedback line. The sensing gate senses a voltage at its input assuming no feedback is applied. Again, the corresponding output of two stacked PMOS transistors is assumed to be connected to the sensing input. Two stacked PMOS transistors generate a high impedance Z-state at its output according to the corresponding gate voltages. Therefore, the feedback line keeps sampling the output and feeding back the output voltage to the sensing input. Consequently, the feedback configuration provides the initial loop condition, which is affected by the midpoint voltage decided by the device aspect ratios of the sensing gate before normal operation starts.

Abstract: The four types of the zero idle time Z-state circuits are presented with an improvement in productivity, cost, chip area, power consumption, and design time. The zero idle time Z-state circuits basically include a sensing gate, two stacked PMOS transistors, and a feedback line. The sensing gate senses a voltage at its input assuming no feedback is applied. Again, the corresponding output of two stacked PMOS transistors is assumed to be connected to the sensing input. Two stacked PMOS transistors generate a high impedance Z-state at its output according to the corresponding output of the sensing gate. Therefore, the feedback line keeps sampling the output and feeding back the output voltage to the sensing input. Consequently, the feedback configuration provides the initial output voltage, which is the midpoint voltage decided by the device aspect ratios of the sensing gate before normal operation starts in all three systems such as all kinds of phase-locked loops, delay-locked loops, and switching regulators.

Abstract: The variable start-up circuits basically include a sensor, triggering transistors, current mirror, current source, an N-bit triggering circuit array, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensor, the output voltage of the sensor turns on the triggering transistors, which provide a total current to its output through the current mirror until the voltage at feedback reaches the midpoint voltage. The time to reach the midpoint voltage at a load is simply equal to the charge stored at the load divided by the total current, which is controlled by an N-bit digital input and a device aspect ratio of each triggering transistor. Consequently, all variable start-up circuits provide an output voltage level closer to the output voltage level that reaches the equilibrium according to schedule.