Patents by Inventor Sang-bom Kang
Sang-bom Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11127739Abstract: A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.Type: GrantFiled: July 5, 2018Date of Patent: September 21, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hye-Lan Lee, Sang-Bom Kang, Jae-Jung Kim, Moon-Kyu Park, Jae-Yeol Song, June-Hee Lee, Yong-Ho Ha, Sang-Jin Hyun
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Patent number: 10847454Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.Type: GrantFiled: December 16, 2019Date of Patent: November 24, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Eui Bok Lee, Deok Young Jung, Sang Bom Kang, Doo-Hwan Park, Jong Min Baek, Sang Hoon Ahn, Hyeok Sang Oh, Woo Kyung You
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Patent number: 10840374Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.Type: GrantFiled: July 3, 2018Date of Patent: November 17, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chung-Hwan Shin, Sang-Bom Kang, Dae-Yong Kim, Jeong-Ik Kim, Chul-Sung Kim, Je-Hyung Ryu, Sang-Woo Lee, Hyo-Seok Choi
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Publication number: 20200118926Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Eui Bok LEE, Deok Young JUNG, Sang Bom KANG, Doo-Hwan PARK, Jong Min BAEK, Sang Hoon AHN, Hyeok Sang OH, Woo Kyung YOU
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Patent number: 10510658Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.Type: GrantFiled: July 19, 2018Date of Patent: December 17, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Eui Bok Lee, Deok Young Jung, Sang Bom Kang, Doo-Hwan Park, Jong Min Baek, Sang Hoon Ahn, Hyeok Sang Oh, Woo Kyung You
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Patent number: 10388563Abstract: A semiconductor device includes a lower layer, an upper layer on the lower layer, a contact between the lower layer and the upper layer, the contact electrically connects the lower layer and the upper layer, a capping pattern wrapping around the contact and covering an upper surface of the contact, a barrier layer wrapping around the capping pattern and covering a lower surface of the capping pattern and a lower surface of the contact, and an interlayer insulating layer between the lower layer and the upper layer, the interlayer insulating layer wrapping around the barrier layer and exposing an upper surface of the capping pattern, wherein the capping pattern includes a material having an etching selectivity with respect to an oxide.Type: GrantFiled: August 3, 2017Date of Patent: August 20, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Rak Hwan Kim, Byung Hee Kim, Sang Bom Kang, Jong Jin Lee, Eun Ji Jung
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Publication number: 20190181088Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.Type: ApplicationFiled: July 19, 2018Publication date: June 13, 2019Inventors: Eui Bok Lee, Deok Young JUNG, Sang Bom KANG, Doo-Hwan PARK, Jong Min BAEK, Sang Hoon AHN, Hyeok Sang OH, Woo Kyung YOU
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Publication number: 20180331100Abstract: A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.Type: ApplicationFiled: July 5, 2018Publication date: November 15, 2018Inventors: Hye-Lan Lee, Sang-Bom Kang, Jae-Jung Kim, Moon-Kyu Park, Jae-Yeol Song, June-Hee Lee, Yong-Ho Ha, Sang-Jin Hyun
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Publication number: 20180331218Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.Type: ApplicationFiled: July 3, 2018Publication date: November 15, 2018Inventors: Chung-Hwan Shin, Sang-Bom Kang, Dae-Yong Kim, Jeong-lk Kim, Chul-Sung Kim, Je-Hyung Ryu, Sang-Woo Lee, Hyo-Seok Choi
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Patent number: 10043902Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.Type: GrantFiled: December 9, 2015Date of Patent: August 7, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Chung-Hwan Shin, Sang-Bom Kang, Dae-Yong Kim, Jeong-Ik Kim, Chul-Sung Kim, Je-Hyung Ryu, Sang-Woo Lee, Hyo-Seok Choi
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Publication number: 20180166334Abstract: A semiconductor device includes a lower layer, an upper layer on the lower layer, a contact between the lower layer and the upper layer, the contact electrically connects the lower layer and the upper layer, a capping pattern wrapping around the contact and covering an upper surface of the contact, a barrier layer wrapping around the capping pattern and covering a lower surface of the capping pattern and a lower surface of the contact, and an interlayer insulating layer between the lower layer and the upper layer, the interlayer insulating layer wrapping around the barrier layer and exposing an upper surface of the capping pattern, wherein the capping pattern includes a material having an etching selectivity with respect to an oxide.Type: ApplicationFiled: August 3, 2017Publication date: June 14, 2018Inventors: Rak Hwan KIM, Byung Hee KIM, Sang Bom KANG, Jong Jin LEE, Eun Ji JUNG
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Publication number: 20160233334Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.Type: ApplicationFiled: December 9, 2015Publication date: August 11, 2016Inventors: Chung-Hwan Shin, Sang-Bom Kang, Dae-Yong Kim, Jeong-Ik Kim, Chul-Sung Kim, Je-Hyung Ryu, Sang-Woo Lee, Hyo-Seok Choi
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Patent number: 9305921Abstract: A semiconductor device including: a first gate pattern disposed in a peripheral region of a substrate; a second gate pattern disposed in a cell region of the substrate; a first insulator formed on sidewalls of the first gate pattern; and a second insulator formed on sidewalls of the second gate pattern, wherein a dielectric constant of the first insulator is different from a dielectric constant of the second insulator, and wherein a height of the second insulator is greater than a height of the second gate pattern.Type: GrantFiled: December 10, 2014Date of Patent: April 5, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Chan Lee, Seung-Jae Lee, Sang-Bom Kang, Dae-Young Kwak, Myeong-Cheol Kim, Yong-Ho Jeon
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Patent number: 9299811Abstract: Semiconductor devices may include first and second fins that protrude from a substrate, extend in a first direction, and are separated from each other in the first direction. Semiconductor devices may also include a field insulating layer that is disposed between the first and second fins to extend in a second direction intersecting the first direction, an etch-stop layer pattern that is formed on the field insulating layer and a dummy gate structure that is formed on the etch-stop layer pattern.Type: GrantFiled: October 21, 2014Date of Patent: March 29, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Wook-Je Kim, Jae-Yup Chung, Jong-Seo Hong, Cheol Kim, Hee-Soo Kang, Hyun-Jo Kim, Hee-Don Jeong, Soo-Hun Hong, Sang-Bom Kang, Myeong-Cheol Kim, Young-Su Chung
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Patent number: 9240323Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.Type: GrantFiled: March 7, 2013Date of Patent: January 19, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Chung-Hwan Shin, Sang-Bom Kang, Dae-Yong Kim, Jeong-Ik Kim, Chul-Sung Kim, Je-Hyung Ryu, Sang-Woo Lee, Hyo-Seok Choi
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Patent number: 9190410Abstract: A method of manufacturing a semiconductor device includes forming first and second gate structures on a substrate in first and second regions, respectively, forming a first capping layer on the substrate by a first high density plasma process, such that the first capping layer covers the first and second gate structures except for sidewalls thereof, removing a portion of the first capping layer in the first region, removing an upper portion of the substrate in the first region using the first gate structure as an etching mask to form a first trench, and forming a first epitaxial layer to fill the first trench.Type: GrantFiled: August 22, 2014Date of Patent: November 17, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung-Hun Lee, Byeong-Chan Lee, Sang-Bom Kang
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Patent number: 9112054Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An epitaxial layer is formed on a top surface of the substrate adjacent to the gate structure. An elevated source/drain (ESD) layer and an impurity region are formed by implanting impurities and carbon in the epitaxial layer and an upper portion of the substrate using the gate structure as an ion implantation mask. A metal silicide layer is formed on the ESD layer.Type: GrantFiled: July 13, 2011Date of Patent: August 18, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwan-Heum Lee, Wook-Je Kim, Soon-Wook Jung, Sang-Bom Kang, Ki-Hong Kim
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Publication number: 20150145056Abstract: A semiconductor device including: a first gate pattern disposed in a peripheral region of a substrate; a second gate pattern disposed in a cell region of the substrate; a first insulator formed on sidewalls of the first gate pattern; and a second insulator formed on sidewalls of the second gate pattern, wherein a dielectric constant of the first insulator is different from a dielectric constant of the second insulator, and wherein a height of the second insulator is greater than a height of the second gate pattern.Type: ApplicationFiled: December 10, 2014Publication date: May 28, 2015Inventors: Jung-Chan Lee, Seung-Jae Lee, Sang-Bom Kang, Dae-Young Kwak, Myeong-Cheol Kim, Yong-Ho Jeon
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Publication number: 20150147860Abstract: Semiconductor devices may include first and second fins that protrude from a substrate, extend in a first direction, and are separated from each other in the first direction. Semiconductor devices may also include a field insulating layer that is disposed between the first and second fins to extend in a second direction intersecting the first direction, an etch-stop layer pattern that is formed on the field insulating layer and a dummy gate structure that is formed on the etch-stop layer pattern.Type: ApplicationFiled: October 21, 2014Publication date: May 28, 2015Inventors: Wook-Je Kim, Jae-Yup Chung, Jong-Seo Hong, Cheol Kim, Hee-Soo Kang, Hyun-Jo Kim, Hee-Don Jeong, Soo-Hun Hong, Sang-Bom Kang, Myeong-Cheol Kim, Young-Su Chung
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Publication number: 20140374840Abstract: A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.Type: ApplicationFiled: June 23, 2014Publication date: December 25, 2014Inventors: Hye-Lan Lee, Sang-Bom Kang, Jae-Jung Kim, Moon-Kyu Park, Jae-Yeol Song, June-Hee Lee, Yong-Ho Ha, Sang-Jin Hyun