Abstract: A semiconductor device is provided. The semiconductor device includes: a first substrate; an active pattern extending on the first substrate; a gate electrode extending on the active pattern; a source/drain region on the active pattern; a first interlayer insulating layer on the source/drain region; a sacrificial layer on the first substrate; a lower wiring layer on a lower surface of the sacrificial layer; a through via trench extending to the lower wiring layer by passing through the first interlayer insulating layer and the sacrificial layer in a vertical direction; a through via inside the through via trench and connected to the lower wiring layer; a recess inside the sacrificial layer and protruding from a sidewall of the through via trench in the second horizontal direction; and a through via insulating layer extending along the sidewall of the through via trench and into the recess.

Abstract: A semiconductor device is provided. The semiconductor device comprises a first wiring structure which includes a first material, and has a first width on a lowest surface in a first direction and a second wiring structure which includes a second material, is spaced apart from the first wiring structure in the first direction, and has a second width smaller than the first width on a lowest surface in the first direction, wherein a highest surface of the first wiring structure has a third width smaller than the first width in the first direction, and a highest surface of the second wiring structure has a fourth width smaller than the second width in the first direction.

Abstract: A semiconductor device includes a substrate, a first interlayer insulating layer on the substrate, a lower wiring pattern inside the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer, a second interlayer insulating layer on the etch stop layer, a via trench inside the second interlayer insulating layer and the etch stop layer and that extends to the lower wiring pattern, a via inside the via trench and that is in contact with the second interlayer insulating layer and is formed of a single film, an upper wiring trench formed inside the second interlayer insulating layer on the via, and an upper wiring pattern inside the upper wiring trench and that includes an upper wiring barrier layer and an upper wiring filling layer on the upper wiring barrier layer An upper surface of the via is in contact with the upper wiring filling layer.