Abstract: Disclosed is an operating method of an electronic device which includes a processor executing a semiconductor layout simulation module based on machine learning. The operating method includes receiving, at the semiconductor layout simulation module executed by the processor, a layout image, inferring a wafer image based on the layout image and a fabrication device information image of a semiconductor fabrication device fabricating a semiconductor integrated circuit based on a final layout image, adjusting the layout image when the wafer image is not acceptable, and confirming the layout image as the final layout image when the wafer image is acceptable.

Abstract: Disclosed are a method of forming an optical proximity correction (OPC) model and/or a method of fabricating a semiconductor device using the same. The method of forming the OPC model may include obtaining a scanning electron microscope (SEM) image, which is an average image of a plurality of images taken using one or more scanning electron microscopes, and a graphic data system (GDS) image, which is obtained by imaging a designed layout, aligning the SEM image and the GDS image, performing an image filtering process on the SEM image, extracting a contour from the SEM image, and verifying the contour. The verifying of the contour may be performed using a genetic algorithm. Variables in the genetic algorithm may include first parameters related to the image alignment process, second parameters related to the image filtering process, and third parameters related to a critical dimension (CD) measurement process.

Abstract: Provided is an extreme ultraviolet (EUV) mask manufacturing method of forming an optimum pattern on a wafer by efficiently reflecting a mask topography effect or a coupling effect between edges of a pattern and improving the accuracy of an EUV mask image. The EUV mask manufacturing method includes performing an optical proximity correction (OPC) method for obtaining EUV mask design data, transferring the EUV mask design data as mask tape-out (MTO) design data, preparing mask data based on the MTO design data, and completing an EUV mask by exposing an EUV mask substrate based on the mask data, wherein the performing of the OPC method applies a coupling filter to both a first case in which angles of an edge pair satisfy |?1??2|=0, and a second case in which angles of an edge pair satisfy 0<|?1??2|?an angle tolerance.

Abstract: A semiconductor device fabrication method includes providing a layout; performing an optical proximity correction on the layout to generate a corrected layout; and forming a photoresist pattern on a substrate by using a photomask fabricated with the corrected layout. The OPC may include: extracting edges of a pattern, the edges including a first edge and a second edge that converge to define a corner; generating a thin mask image by applying a thin mask approximation to the pattern; changing the first edge and the second edge into a first stepped edge and a second stepped edge; and applying a three-dimensional filter to the first and second stepped edges to generate an optical image including the corrected layout of the pattern to which the 3D filter is applied from the thin mask image.

Abstract: A semiconductor device fabrication method includes providing a layout; performing an optical proximity correction on the layout to generate a corrected layout; and forming a photoresist pattern on a substrate by using a photomask fabricated with the corrected layout. The OPC may include: extracting edges of a pattern, the edges including a first edge and a second edge that converge to define a corner; generating a thin mask image by applying a thin mask approximation to the pattern; changing the first edge and the second edge into a first stepped edge and a second stepped edge; and applying a three-dimensional filter to the first and second stepped edges to generate an optical image including the corrected layout of the pattern to which the 3D filter is applied from the thin mask image.

Abstract: A method for manufacturing a semiconductor device includes performing an optical proximity correction (OPC) process on a designed layout based on a final model signal obtained according to an OPC modeling process to generate a corrected layout, the OPC modeling process including, selecting a transmittance value of a sub-layout pattern of a sub-layout included in a target layout, the transmittance value being a parameter of an OPC model and representing an intensity of light that transmits through a photomask, and generating a final model signal based on the transmittance value of the sub-layout pattern, and forming a photoresist pattern on a substrate using the photomask generated based on the corrected layout.

Abstract: A method for manufacturing a semiconductor device includes performing an optical proximity correction (OPC) process on a designed layout based on a final model signal obtained according to an OPC modeling process to generate a corrected layout, the OPC modeling process including, selecting a transmittance value of a sub-layout pattern of a sub-layout included in a target layout, the transmittance value being a parameter of an OPC model and representing an intensity of light that transmits through a photomask, and generating a final model signal based on the transmittance value of the sub-layout pattern, and forming a photoresist pattern on a substrate using the photomask generated based on the corrected layout.