Patents by Inventor Sang-Duk Park
Sang-Duk Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240072140Abstract: A semiconductor device includes, first and second source/drain patterns on an active pattern and spaced apart from each other, a first source/drain contact on the first source/drain pattern and including a first source/drain barrier film and a first source/drain filling film on the first source/drain barrier film, a second source/drain contact on the second source/drain pattern, and a gate structure on the active pattern between the first and second source/drain contacts and including a gate electrode, wherein a top surface of the first source/drain contact is lower than a top surface of the gate structure, and a height from a top surface of the active pattern to a top surface of the first source/drain barrier film is less than a height from the top surface of the active pattern to a top surface of the first source/drain filling film.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Inventors: Won Hyuk Lee, Jong Chul Park, Sang Duk Park, Hong Sik Shin, Do Haing Lee
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Patent number: 11917875Abstract: A display device includes a substrate including an active area having pixels and a non-active area including a pad region. A pad electrode is disposed in the pad region and includes a first pad electrode and a second pad electrode disposed on the first pad electrode. A first insulating pattern is interposed between the first and second pad electrodes. In a plan view, the first insulating pattern is positioned inside the first pad electrode, and a portion of the second pad electrode overlapping the first insulating pattern protrudes further from the substrate in a thickness direction than a portion of the second pad electrode not overlapping the first insulating pattern. The second pad electrode directly contacts a portion of the upper surface of the first pad electrode. In a plan view, an area of the second pad electrode is greater than an area of the first pad electrode.Type: GrantFiled: December 29, 2021Date of Patent: February 27, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Ki Kyung Youk, Chan Jae Park, Min Soo Kim, Yoon A Kim, Sang Duk Lee, Chel Gou Lim
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Patent number: 11848364Abstract: A semiconductor device includes, first and second source/drain patterns on an active pattern and spaced apart from each other, a first source/drain contact on the first source/drain pattern and including a first source/drain barrier film and a first source/drain filling film on the first source/drain barrier film, a second source/drain contact on the second source/drain pattern, and a gate structure on the active pattern between the first and second source/drain contacts and including a gate electrode, wherein a top surface of the first source/drain contact is lower than a top surface of the gate structure, and a height from a top surface of the active pattern to a top surface of the first source/drain barrier film is less than a height from the top surface of the active pattern to a top surface of the first source/drain filling film.Type: GrantFiled: May 12, 2021Date of Patent: December 19, 2023Inventors: Won Hyuk Lee, Jong Chul Park, Sang Duk Park, Hong Sik Shin, Do Haing Lee
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Publication number: 20220109055Abstract: A semiconductor device includes, first and second source/drain patterns on an active pattern and spaced apart from each other, a first source/drain contact on the first source/drain pattern and including a first source/drain barrier film and a first source/drain filling film on the first source/drain barrier film, a second source/drain contact on the second source/drain pattern, and a gate structure on the active pattern between the first and second source/drain contacts and including a gate electrode, wherein a top surface of the first source/drain contact is lower than a top surface of the gate structure, and a height from a top surface of the active pattern to a top surface of the first source/drain barrier film is less than a height from the top surface of the active pattern to a top surface of the first source/drain filling film.Type: ApplicationFiled: May 12, 2021Publication date: April 7, 2022Inventors: Won Hyuk Lee, Jong Chul Park, Sang Duk Park, Hong Sik Shin, Do Haing Lee
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Patent number: 10224343Abstract: There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure.Type: GrantFiled: January 12, 2018Date of Patent: March 5, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Bo Soon Kim, Hyun Ji Kim, Jeong Yun Lee, Gi Gwan Park, Sang Duk Park, Young Mook Oh, Yong Seok Lee
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Publication number: 20180158836Abstract: There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure.Type: ApplicationFiled: January 12, 2018Publication date: June 7, 2018Inventors: Bo Soon KIM, Hyun Ji KIM, Jeong Yun LEE, Gi Gwan PARK, Sang Duk PARK, Young Mook OH, Yong Seok LEE
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Patent number: 9899416Abstract: There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure.Type: GrantFiled: January 11, 2017Date of Patent: February 20, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Bo Soon Kim, Hyun Ji Kim, Jeong Yun Lee, Gi Gwan Park, Sang Duk Park, Young Mook Oh, Yong Seok Lee
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Publication number: 20170200738Abstract: There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure.Type: ApplicationFiled: January 11, 2017Publication date: July 13, 2017Inventors: Bo Soon KIM, Hyun Ji KIM, Jeong Yun LEE, Gi Gwan PARK, Sang Duk PARK, Young Mook OH, Yong Seok LEE
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Publication number: 20160190142Abstract: In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and the second gate electrode being formed in a first region and a second region of the substrate, respectively. A conductive buffer layer is formed along sidewalls of the first gate electrode and the second gate electrode and on upper surfaces of the first gate electrode and second gate electrode. A first mask pattern covering the first region of the substrate on the buffer layer is formed. A first impurity region is formed in the substrate at sides of the second gate electrode using the first mask pattern as a mask of an ion implantation process.Type: ApplicationFiled: March 4, 2016Publication date: June 30, 2016Inventors: Ju-Youn Kim, Sang-Duk Park, Jae-Kyung Seo, Kwang-Sub Yoon, In-Gu Yoon
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Patent number: 9312188Abstract: In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and the second gate electrode being formed in a first region and a second region of the substrate, respectively. A conductive buffer layer is formed along sidewalls of the first gate electrode and the second gate electrode and on upper surfaces of the first gate electrode and second gate electrode. A first mask pattern covering the first region of the substrate on the buffer layer is formed. A first impurity region is formed in the substrate at sides of the second gate electrode using the first mask pattern as a mask of an ion implantation process.Type: GrantFiled: January 31, 2014Date of Patent: April 12, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-Youn Kim, Sang-Duk Park, Jae-Kyung Seo, Kwang-Sub Yoon, In-Gu Yoon
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Publication number: 20150364574Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure including a dummy gate insulation layer pattern, a dummy gate electrode and a gate mask sequentially stacked are formed on a substrate. An interlayer insulating layer including tonen silazane (TOSZ) is formed on the substrate to cover the dummy gate structure. An upper portion of the interlayer insulating layer is planarized until a top surface of the gate mask is exposed to form an interlayer insulating layer pattern. The exposed gate mask, and the dummy gate electrode and the dummy gate insulation layer pattern under the gate mask are removed to form an opening exposing a top surface of the substrate. The dummy gate insulation layer pattern is removed using an etchant including hydrogen fluoride (HF), but the interlayer insulating layer pattern remains. A gate structure is formed to fill the opening.Type: ApplicationFiled: December 22, 2014Publication date: December 17, 2015Inventors: Ju-Youn KIM, Dong-Hyun ROH, Sang-Duk PARK, Il-Young YOON, Jeong-Nam HAN, Jong-Mil YOUN
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Publication number: 20140370699Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench and a second trench, forming a first conductive layer along sidewall surfaces and bottom surface of the first trench and forming a second conductive layer along sidewall surfaces and bottom surface of the second trench, forming a mask pattern on the second conductive layer, the mask pattern filling the second trench and being a bottom anti-reflective coating (BARC), and removing the first conductive layer using the mask pattern.Type: ApplicationFiled: December 31, 2013Publication date: December 18, 2014Inventors: Ju-Youn Kim, Chul-Woong Lee, Tae-Sun Kim, Sang-Duk Park, Bum-Joon Youn, Tae-Won Ha
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Publication number: 20140370672Abstract: In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and the second gate electrode being formed in a first region and a second region of the substrate, respectively. A conductive buffer layer is formed along sidewalls of the first gate electrode and the second gate electrode and on upper surfaces of the first gate electrode and second gate electrode. A first mask pattern covering the first region of the substrate on the buffer layer is formed. A first impurity region is formed in the substrate at sides of the second gate electrode using the first mask pattern as a mask of an ion implantation process.Type: ApplicationFiled: January 31, 2014Publication date: December 18, 2014Inventors: Ju-Youn Kim, Sang-Duk Park, Jae-Kyung Seo, Kwang-Sub Yoon, In-Gu Yoon
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Publication number: 20110192820Abstract: An atomic layer etching apparatus using reactive radicals and neutral beams and an etching method using the same are provided.Type: ApplicationFiled: February 25, 2010Publication date: August 11, 2011Applicant: SUNGKYUNKWAN UNIVERSITY Foundation for Corporate CollaborationInventors: Geun-Young Yeom, Woong-Sun Lim, Sang-Duk Park, Yi-Yeon Kim, Byoung-Jae Park, Je-Kwan Yeon
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Patent number: 7777178Abstract: A plasma generating apparatus and method using a neutral beam, capable of readily generating plasma at the same gas flow rate by changing the structure of an ion gun, without a separate ignition device, are provided. The apparatus includes a plasma generating part formed of a quartz cup, a radio frequency (RF) applying antenna disposed at the periphery of the plasma generating part, a cooling water supply part disposed at the periphery of the plasma generating part, and an igniter in direct communication with the plasma generating part, wherein a gas for generating plasma is supplied into the igniter, and the igniter has a higher local pressure than the plasma generating part at the same gas flow rate. The ion gun is also cheaper to manufacture since it does not require a separate power supply.Type: GrantFiled: March 23, 2006Date of Patent: August 17, 2010Assignee: Sungyunkwan University Foundation for Corporate CollaborationInventors: Geun-Young Yeom, Sang-Duk Park, Chang-Kwon Oh
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Publication number: 20070221833Abstract: A plasma generating apparatus and method using a neutral beam, capable of readily generating plasma at the same gas flow rate by changing the structure of an ion gun, without a separate ignition device, are provided. The apparatus includes a plasma generating part formed of a quartz cup, a radio frequency (RF) applying antenna disposed at the periphery of the plasma generating part, a cooling water supply part disposed at the periphery of the plasma generating part, and an igniter in direct communication with the plasma generating part, wherein a gas for generating plasma is supplied into the igniter, and the igniter has a higher local pressure than the plasma generating part at the same gas flow rate. The ion gun is also cheaper to manufacture since it does not require a separate power supply.Type: ApplicationFiled: March 23, 2006Publication date: September 27, 2007Applicant: SUNGKYUNKWAN UNIVERSITY Foundation for Corporate CollaborationInventors: Geun-Young YEOM, Sang-Duk PARK, Chang-Kwon OH