Patents by Inventor Sangeetha P. Komanduri

Sangeetha P. Komanduri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240215268
    Abstract: Methods, systems, and devices for a single plug flow for a memory device are described. In some examples, the memory device may include one or more plugs formed above respective bit line plates. The plugs may include a liner and one or more sacrificial materials that are removed during a subsequent etching operation. Accordingly, pillars may be formed above the plugs, and may be generally aligned with the respective bit line plates.
    Type: Application
    Filed: December 20, 2023
    Publication date: June 27, 2024
    Inventors: Zhao Zhao, Trevor J. Plaisted, Stephen W. Russell, Farrell M. Good, Sangeetha P. Komanduri, Sandra L. Tagg, Nathan A. Wilkerson
  • Publication number: 20230260840
    Abstract: A method for mitigating crack propagation during manufacture of semiconductor dies, and associated systems and methods are disclosed herein. The method includes forming holes into a first side of a wafer substrate opposite a second side. The wafer substrate has active components at the second side. Each hole extends from the first side towards the second side an extend to an intermediate depth within the wafer substrate such that a bottom of the holes is spaced vertically apart from the active components on the second side. The holes are configured to inhibit cracks in the wafer substrate from propagating longitudinally across the wafer substrate. The method also includes backgrinding the first side of the wafer substrate to thin the wafer substrate after forming the holes. The method also includes dicing the wafer substrate after backgrinding to separate individual semiconductor dies from each other.
    Type: Application
    Filed: April 24, 2023
    Publication date: August 17, 2023
    Inventors: Wei Yeeng Ng, Rajesh Balachandran, Frank Speetjens, Andrew L. Li, Sukhdeep Kaur, Sangeetha P. Komanduri
  • Patent number: 11637040
    Abstract: A method for mitigating crack propagation during manufacture of semiconductor dies, and associated systems and methods are disclosed herein. The method includes forming holes into a first side of a wafer substrate opposite a second side. The wafer substrate has active components at the second side. Each hole extends from the first side towards the second side an extend to an intermediate depth within the wafer substrate such that a bottom of the holes is spaced vertically apart from the active components on the second side. The holes are configured to inhibit cracks in the wafer substrate from propagating longitudinally across the wafer substrate. The method also includes backgrinding the first side of the wafer substrate to thin the wafer substrate after forming the holes. The method also includes dicing the wafer substrate after backgrinding to separate individual semiconductor dies from each other.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: April 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Wei Yeeng Ng, Rajesh Balachandran, Frank Speetjens, Andrew L. Li, Sukhdeep Kaur, Sangeetha P. Komanduri
  • Publication number: 20220208609
    Abstract: A method for mitigating crack propagation during manufacture of semiconductor dies, and associated systems and methods are disclosed herein. The method includes forming holes into a first side of a wafer substrate opposite a second side. The wafer substrate has active components at the second side. Each hole extends from the first side towards the second side an extend to an intermediate depth within the wafer substrate such that a bottom of the holes is spaced vertically apart from the active components on the second side. The holes are configured to inhibit cracks in the wafer substrate from propagating longitudinally across the wafer substrate. The method also includes backgrinding the first side of the wafer substrate to thin the wafer substrate after forming the holes. The method also includes dicing the wafer substrate after backgrinding to separate individual semiconductor dies from each other.
    Type: Application
    Filed: December 29, 2020
    Publication date: June 30, 2022
    Inventors: Wei Yeeng Ng, Rajesh Balachandran, Frank Speetjens, Andrew L. Li, Sukhdeep Kaur, Sangeetha P. Komanduri