Patents by Inventor Sang-Gyun Lee

Sang-Gyun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11914564
    Abstract: A Merkle tree-based data management method may comprise: aligning data into two-dimensional square matrix; calculating a hash value of each node of the two-dimensional square matrix; calculating hash values of each row of the two-dimensional square matrix; generating an additional column with nodes having the hash values of each row; calculating hash values of each column of the two-dimensional square matrix; generating an additional row with nodes having hash values of each column; and calculating a Merkle root by concatenating the hash values of the additional column and the hash values of the additional row.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: February 27, 2024
    Assignee: Penta Security Inc.
    Inventors: Jin Hyeok Oh, Keon Yun, Sun Woo Yun, Sang Min Lee, Jun Yong Lee, Sang Gyoo Sim, Tae Gyun Kim
  • Patent number: 11037890
    Abstract: A semiconductor assembly with a package on package (POP) structure includes a first semiconductor package having a first lower substrate, a first upper substrate facing the first lower substrate, and a first semiconductor chip mounted on an area of the first lower substrate. The POP structure further includes a second semiconductor package having a second lower substrate stacked on the first semiconductor package and spaced apart from the first semiconductor package, and a second semiconductor chip mounted in an area of the second lower substrate. At least one passive element is disposed in one of the first upper substrate and the second lower substrate and electrically connected to the second semiconductor chip.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: June 15, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki Cheol Bae, Chui Woo Park, Kwang Sub Lee, Sang Gyun Lee, Se Young Jang, Chi Hyun Cho
  • Publication number: 20200098708
    Abstract: A semiconductor assembly with a package on package (POP) structure includes a first semiconductor package having a first lower substrate, a first upper substrate facing the first lower substrate, and a first semiconductor chip mounted on an area of the first lower substrate. The POP structure further includes a second semiconductor package having a second lower substrate stacked on the first semiconductor package and spaced apart from the first semiconductor package, and a second semiconductor chip mounted in an area of the second lower substrate. At least one passive element is disposed in one of the first upper substrate and the second lower substrate and electrically connected to the second semiconductor chip.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Inventors: Ki Cheol BAE, Chul Woo PARK, Kwang Sub LEE, Sang Gyun LEE, Se Young JANG, Chi Hyun CHO
  • Patent number: 10529676
    Abstract: A semiconductor assembly with a package on package (POP) structure includes a first semiconductor package having a first lower substrate, a first upper substrate facing the first lower substrate, and a first semiconductor chip mounted on an area of the first lower substrate. The POP structure further includes a second semiconductor package having a second lower substrate stacked on the first semiconductor package and spaced apart from the first semiconductor package, and a second semiconductor chip mounted in an area of the second lower substrate. At least one passive element is disposed in one of the first upper substrate and the second lower substrate and electrically connected to the second semiconductor chip.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: January 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki Cheol Bae, Chul Woo Park, Kwang Sub Lee, Sang Gyun Lee, Se Young Jang, Chi Hyun Cho
  • Publication number: 20170358544
    Abstract: A semiconductor assembly with a package on package (POP) structure includes a first semiconductor package having a first lower substrate, a first upper substrate facing the first lower substrate, and a first semiconductor chip mounted on an area of the first lower substrate. The POP structure further includes a second semiconductor package having a second lower substrate stacked on the first semiconductor package and spaced apart from the first semiconductor package, and a second semiconductor chip mounted in an area of the second lower substrate. At least one passive element is disposed in one of the first upper substrate and the second lower substrate and electrically connected to the second semiconductor chip.
    Type: Application
    Filed: June 8, 2017
    Publication date: December 14, 2017
    Inventors: Ki Cheol BAE, Chul Woo Park, Kwang Sub Lee, Sang Gyun Lee, Se Young Jang, Chi Hyun Cho
  • Publication number: 20110261925
    Abstract: A grid apparatus of an X-ray detecting apparatus is provided. The grid apparatus includes an X-ray absorbing material for absorbing X-rays that are scattered from an object, and an X-ray passing material formed between the X-ray absorbing materials to allow X-rays to pass therethrough. The X-ray absorbing material and the X-ray passing material form a line pattern forming a predetermined angle with a line pattern of pixels of an X-ray detector. The grid apparatus enables simpler implementation of a grid noise reduction algorithm and reduces the time and labor for reducing grid noise.
    Type: Application
    Filed: October 4, 2010
    Publication date: October 27, 2011
    Applicant: DRTECH Corporation
    Inventors: Dong-Sik KIM, Sang-Gyun LEE, Beom-Jin MOON, Jung-Kee YOON
  • Publication number: 20100051329
    Abstract: Disclosed are a printed circuit board and a method of manufacturing the same. The method in accordance with an embodiment of the present invention includes: forming an electroless plated layer on an insulation layer; and forming a circuit pattern by applying conductive ink on the electroless plated layer through an inkjet method.
    Type: Application
    Filed: April 23, 2009
    Publication date: March 4, 2010
    Inventors: Tae-Hoon KIM, Dong-Hoon Kim, Young-Il Lee, Sang-Gyun Lee, Byung-Ho Jun, Da-Mi Shim