Abstract: For a hot carrier injection tolerant network on chip (NoC) router architecture, a plurality of input buffers receives a plurality of input data bits. A plurality of multiplexers shuffles the plurality of input data bits to output a plurality of shuffled input buffer data bits. A coupling module switches first input buffer data bits at the plurality of input buffers from first shuffled input buffer data bits to second shuffled input buffer data bits using the plurality of multiplexers. A selector selects, using a plurality of decoders, a virtual channel path to a virtual channel of the plurality of virtual channels for the shuffled input buffer data bits. A connection module switches the second shuffled input buffer data bits from a first virtual channel to a second virtual channel of the plurality of virtual channels using the plurality of decoders.

Abstract: For runtime detection of a bandwidth denial attack from a rogue NoC. The apparatus includes a processor and a memory storing code executable by the processor. The processor generates a plurality of proximal analogous packets each corresponding to a given packet traversing a multiprocessor system-on-chips (MPSoC). Each proximal analogous packet includes one or more of a proximal source modified from a given packet source and a proximal destination modified from a given packet destination. The processor further compares traversal latencies between each proximal analogous packet/given packet pair. In addition, the processor detects a rogue interconnect in response to aggregate variations in the traversal latencies.

Abstract: For an error resilient pipeline, a Dynamically Adaptable Resilient Pipeline (DARP) controller determines a minimum error pipeline stage of a processor instruction pipeline with a minimum number of errors. In addition, the DARP controller determines a maximum error pipeline stage of the instruction pipeline with a maximum number of errors. The DARP controller increases a clock frequency for the instruction pipeline if the minimum number of errors of the minimum error pipeline stage is zero and the maximum number of errors of the maximum error pipeline stage does not exceed an error threshold. In addition, the DARP controller decreases the clock frequency if the minimum number of errors exceeds an error constant.

Abstract: For mitigating a compromised network-on-chip, code appends a node identifier of a destination node to a packet transmitted in a multiprocessor system-on-chip (MPSOC). The MPSOC may include third-party components such as a network-on-chip. The code may detect a copy of the packet from the node identifier. In addition, the code may drop the copy of the packet in response to the copy of the packet being routed to an unintended node.

Abstract: For a hot carrier injection tolerant network on chip (NoC) router architecture, a plurality of input buffers receives a plurality of input data bits. A plurality of multiplexers shuffles the plurality of input data bits to output a plurality of shuffled input buffer data bits. A coupling module switches first input buffer data bits at the plurality of input buffers from first shuffled input buffer data bits to second shuffled input buffer data bits using the plurality of multiplexers. A selector selects, using a plurality of decoders, a virtual channel path to a virtual channel of the plurality of virtual channels for the shuffled input buffer data bits. A connection module switches the second shuffled input buffer data bits from a first virtual channel to a second virtual channel of the plurality of virtual channels using the plurality of decoders.

Abstract: For runtime detection of a bandwidth denial attack from a rogue NoC. The apparatus includes a processor and a memory storing code executable by the processor. The processor generates a plurality of proximal analogous packets each corresponding to a given packet traversing a multiprocessor system-on-chips (MPSoC). Each proximal analogous packet includes one or more of a proximal source modified from a given packet source and a proximal destination modified from a given packet destination. The processor further compares traversal latencies between each proximal analogous packet/given packet pair. In addition, the processor detects a rogue interconnect in response to aggregate variations in the traversal latencies.

Abstract: For global routing using a graphics processing unit (GPU), a method routes a net of node interconnections for a semiconductor design. In addition, the method decomposes the net into subnets. Each subnet has no shared paths. The method further identifies a congested region of the routed net that exceeds routing capacities. In addition, the method correlates the congested region with a plurality of first subnets with workloads within the congested region. The method routes the subnets in parallel using the GPU.

Abstract: For aging-aware routing, an aging module calculates an aging score for links and routers in a Network-on-Chip for a previous epoch. A routing module dynamically routes a flow through the links and the routers to satisfy routing criteria including a least total aging score for the links and the routers of the flow.

Abstract: For mapping a sustainable, differentially reliable architecture for dark silicon, a calculation module calculates an expected energy efficiency for a prior mapping of process threads for a plurality of cores. The calculation module further calculates a workload acceptance capacity (WAC) from degradation rates for the plurality of cores. A map module maps the process threads to the plurality of cores based on at least one of the expected energy efficiency and the WAC to satisfy a mapping policy. A specified number of the plurality of cores is not powered.

Abstract: For mitigating a compromised network-on-chip, code appends a node identifier of a destination node to a packet transmitted in a multiprocessor system-on-chip (MPSOC). The MPSOC may include third-party components such as a network-on-chip. The code may detect a copy of the packet from the node identifier. In addition, the code may drop the copy of the packet in response to the copy of the packet being routed to an unintended node.

Abstract: For an error resilient pipeline, a Dynamically Adaptable Resilient Pipeline (DARP) controller determines a minimum error pipeline stage of a processor instruction pipeline with a minimum number of errors. In addition, the DARP controller determines a maximum error pipeline stage of the instruction pipeline with a maximum number of errors. The DARP controller increases a clock frequency for the instruction pipeline if the minimum number of errors of the minimum error pipeline stage is zero and the maximum number of errors of the maximum error pipeline stage does not exceed an error threshold. In addition, the DARP controller decreases the clock frequency if the minimum number of errors exceeds an error constant.

Abstract: For dynamic memory relocation, a tracking module tracks accesses to a plurality of memory devices. Each of the plurality of memory devices is in communication with one memory controller of a plurality of memory controllers embedded in a computing device comprising a plurality of nodes. A migration module migrates first data from a first memory device in communication with a first memory controller to a second memory device in communication with a second memory controller.

Abstract: For predicting timing violations, a prediction module predicts a timing violation for a first instruction in a semiconductor device in response to use by the first instruction of a specified sensitized path. The prediction module further mitigates the predicted timing violation.

Abstract: For mapping a sustainable, differentially reliable architecture for dark silicon, a calculation module calculates an expected energy efficiency for a prior mapping of process threads for a plurality of cores. The calculation module further calculates a workload acceptance capacity (WAC) from degradation rates for the plurality of cores. A map module maps the process threads to the plurality of cores based on at least one of the expected energy efficiency and the WAC to satisfy a mapping policy. A specified number of the plurality of cores is not powered.

Abstract: For global routing using a graphics processing unit (GPU), a method routes a net of node interconnections for a semiconductor design. In addition, the method decomposes the net into subnets. Each subnet has no shared paths. The method further identifies a congested region of the routed net that exceeds routing capacities. In addition, the method correlates the congested region with a plurality of first subnets with workloads within the congested region. The method routes the subnets in parallel using the GPU.

Abstract: For dynamic memory relocation, a tracking module tracks accesses to a plurality of memory devices. Each of the plurality of memory devices is in communication with one memory controller of a plurality of memory controllers embedded in a computing device comprising a plurality of nodes. A migration module migrates first data from a first memory device in communication with a first memory controller to a second memory device in communication with a second memory controller.

Abstract: For a hot carrier injection tolerant network on chip (NoC) router architecture, a coupling module modifies couplings of connecting wires to input buffer data bits in an NoC data channel. A connection module modifies connection points of an input buffer to the connecting wires.

Abstract: For multicore power performance management, a first core has a first architecture and is designed for a first voltage-frequency domain. A second core has the first architecture and that is designed for a second voltage-frequency domain.

Abstract: For predicting timing violations, a prediction module predicts a timing violation for a first instruction in a semiconductor device in response to use by the first instruction of a specified sensitized path. The prediction module further mitigates the predicted timing violation.

Abstract: Circuit floorplanning is performed on a combination central processing unit and multiprocessor. A B*-tree data structure of a floorplan and circuit related constants reside in a central processing unit data storage. The B* tree structure of a floorplan along and said circuit related constants are copied to a multiprocessor data storage where multiple thread blocks, each consisting of a single thread, copy the tree to their own shared memories. The multiprocessor concurrently evaluates different moves in different thread blocks. The multiprocessor then evaluates objective function results and stores those results. The best result for floorplanning is selected from the multiple circuit evaluations.