Abstract: A file protection method of a computer apparatus including a processor, the method including extracting classes from an executable file of a package file, classifying the classes into class groups, adding a loading code to a first class group among the class groups, the loading code configured to cause sequential loading of the class groups to a memory in a random loading order in response to execution of the package file, adding an integrity code to a second class group among the class groups, the integrity code configured to verify an integrity of a corresponding class group among the class groups or a previous class group among the class groups, the previous class group including the loading code configured to cause the corresponding class group to load, and regenerating the package file using the class groups after the adding the loading code and the adding the integrity code.

Abstract: A nonvolatile memory device includes a plurality of memory blocks vertically arranged, first and second row decoder groups configured to couple first and second local global word lines and the word lines of upper memory blocks among the plurality of memory blocks, third and fourth row decoder groups configured to couple third and fourth local global word lines and the word lines of lower memory blocks among the plurality of memory blocks, a first local decoder switch configured to couple a plurality of global lines and the first or second local global word lines, a second local decoder switch configured to couple the plurality of global lines and the third or fourth local global word lines, and a high voltage generator configured to supply operating voltages to the plurality of global word lines.

Abstract: A block decoder of a flash memory device includes a discharge control unit configured to output a discharge signal in response to a program precharge signal and one or more of a number of address signals, and a selection line control unit configured to apply a ground voltage to source and drain selection lines of memory blocks in response to the discharge signal.

Abstract: A nonvolatile memory device includes a plurality of memory blocks vertically arranged, first and second row decoder groups configured to couple first and second local global word lines and the word lines of upper memory blocks among the plurality of memory blocks, third and fourth row decoder groups configured to couple third and fourth local global word lines and the word lines of lower memory blocks among the plurality of memory blocks, a first local decoder switch configured to couple a plurality of global lines and the first or second local global word lines, a second local decoder switch configured to couple the plurality of global lines and the third or fourth local global word lines, and a high voltage generator configured to supply operating voltages to the plurality of global word lines.

Abstract: A block decoder of a semiconductor memory device includes a control signal generation circuit configured to generate an initial control signal and a block selection control signal in response to memory block selection addresses, an output node control circuit configured to set up an initial voltage of an output node in response to the initial control signal, and a block selection signal generation circuit configured to generate a block selection signal by raising a potential of the output node in response to the block selection control signal and the initial voltage of the output node.

Abstract: A power-on reset signal generation circuit of a semiconductor memory apparatus includes an external voltage level detector configured to detect an external voltage and generate an external voltage detection signal; a band gap voltage generation unit configured to generate a band gap voltage in response to the external voltage detection signal; a level detection voltage dividing unit configured to divide the external voltage depending upon a level of the band gap voltage and generate a division voltage; and a power-on reset signal generation unit configured to compare the level of the band gap voltage with a level of the division voltage and generate a power-on reset signal.

Abstract: A block decoder of a semiconductor memory device includes a control signal generation circuit configured to generate an initial control signal and a block selection control signal in response to memory block selection addresses, an output node control circuit configured to set up an initial voltage of an output node in response to the initial control signal, and a block selection signal generation circuit configured to generate a block selection signal by raising a potential of the output node in response to the block selection control signal and the initial voltage of the output node.

Abstract: A power-on reset signal generation circuit of a semiconductor memory apparatus includes an external voltage level detector configured to detect an external voltage and generate an external voltage detection signal; a band gap voltage generation unit configured to generate a band gap voltage in response to the external voltage detection signal; a level detection voltage dividing unit configured to divide the external voltage depending upon a level of the band gap voltage and generate a division voltage; and a power-on reset signal generation unit configured to compare the level of the band gap voltage with a level of the division voltage and generate a power-on reset signal.

Abstract: A block decoder of a flash memory device includes a discharge control unit configured to output a discharge signal in response to a program precharge signal and one or more of a number of address signals, and a selection line control unit configured to apply a ground voltage to source and drain selection lines of memory blocks in response to the discharge signal.

Abstract: A packaged multi die device includes at least one memory die. The one or more of the memory dice includes a memory function circuit configured to program or read data, a logic circuit configured to control the program operation and the read operation of the memory function circuit in accordance with an inputted operation command, and a power supplying circuit configured to provide a power corresponding to an operation mode to the memory function circuit, and apply an extra power to the logic circuit.

Abstract: A TOE apparatus and a method for transferring a packet applying the TOE have developed. the device comprises that an embedded processor for receiving information on an address and size of physical memory and generating a prototype header according to contents of the received information; and Gigabit Ethernet for generating header information of a packet using the prototype header, receiving data according to the address and size of the physical memory included in the information received from a host device through a main PCI bus, a PCI-to-PCI bridge, and a sub PCI bus, and adding the header information to the data, so as to transmit the data to a network.

Abstract: A packaged multi die device includes at least one memory die. The one or more of the memory dice includes a memory function circuit configured to program or read data, a logic circuit configured to control the program operation and the read operation of the memory function circuit in accordance with an inputted operation command, and a power supplying circuit configured to provide a power corresponding to an operation mode to the memory function circuit, and apply an extra power to the logic circuit.

Abstract: A circuit for generating a step-up voltage, in which it can reduce ripples. The circuit includes a high voltage transfer switch, a high voltage switching unit that pumps a high voltage in response to a clock signal and switches the high voltage transfer switch, a high voltage switching controller, which compares a feedback voltage generated by dividing an output signal of the high voltage transfer switch and a variable reference voltage, generates an internal clock signal using the comparison result and the clock signal, and controls the switching of the high voltage transfer switch in response to the comparison result, and a step-up voltage generator that pumps the high voltage in response to the internal clock signal and a plurality of step-up reference voltages and generates an internal step-up voltage. The high voltage transfer switch outputs the internal step-up voltage in response to the output signal of the high voltage switching unit.

Abstract: An apparatus with integrated RFID reading/internet communication functions and a method thereof are disclosed. An apparatus with integrated RFIF reading/internet communication functions includes a RFID read part comprising a RF module controller that controls a RFID module for receiving/transmit data from a RFID tag, a first processor core that controls an operation of the RFID read part and that sends data, and a first dynamic memory controller that controls a first dynamic memory in communication with the first processor core; and an internet communication part comprising an Ethernet controller that performs internet communication based on an Ethernet interface, a second processor core that controls an operation of the internet communication part and that sends data together with the RFID read part, and a second dynamic memory controller that controls a second dynamic memory in communication with the second processor core.