Abstract: Provided is a layout library having a plurality of unit layouts in which the same flip-flop circuit is implemented. In the layout library, at least two unit layouts have mutually different arrangement structures. Therefore, coupling capacitances seen at an equal node with respect to the two flip-flop circuits appear to be different from each other. A semiconductor designer can select a layout in which a desired coupling capacitance is set through wiring, and through this, can adopt a required flip-flop circuit.

Abstract: A method of testing a semiconductor device including applying a reference test pattern to the semiconductor device in which a preset number of power pins of the semiconductor device are supplied with current, incrementally disconnecting the power pins from the current to set a number of removal power pins, and determining a final number of power pins which represents a minimum number of power pins with which the semiconductor device operates normally. The method additionally includes applying a delay test pattern to the semiconductor device to set a cycle of the delay test pattern corresponding to the number of removal power pins to reduce or prevent an overkill phenomenon.

Abstract: Provided is a layout library having a plurality of unit layouts in which the same flip-flop circuit is implemented. In the layout library, at least two unit layouts have mutually different arrangement structures. Therefore, coupling capacitances seen at an equal node with respect to the two flip-flop circuits appear to be different from each other. A semiconductor designer can select a layout in which a desired coupling capacitance is set through wiring, and through this, can adopt a required flip-flop circuit.

Abstract: A method of testing a semiconductor device is provided. In order to provide the same conditions and application of electrical power as a test process in which characteristic functions of a semiconductor device are tested, the number of removal power pins is set. The final number of power pins that can be provided during a normal operation is determined by setting the number of removal power pins. The final number of power pins represents the minimum number of power pins that are requested to be connected for the normal operation of the semiconductor device, and is met by removing a timing margin during the operation of the semiconductor device. Afterwards, a delay test pattern that can be used during a scan mode is applied. When it is determined to be defective by the delay test pattern, a cycle of the delay test pattern is increased.

Abstract: A boundary scan test system including a transmitter and a receiver. The system performs DC and AC boundary scan testing of the interconnections between devices. The system addresses fault masking that can occur during testing. Of concern are AC coupled interconnections while providing IEEE 1149.1 DC test compatibility. The test receiver includes an input test buffer and an interface mechanism. The input test buffer has a built-in null detection capability. The interface mechanism includes a technology mapper, one or more detectors, and an integrator. The receiver provides at least partial, if not complete, coverage for at least one of five fault syndromes that can result from single defect conditions in the system.

Abstract: An AC boundary scan cell is disclosed. For one embodiment the AC boundary scan cell includes a first multiplexer, a second multiplexer, a first data shift register, a second data register, an XOR logic gate, and a third multiplexer. For one such embodiment the AC boundary scan cell includes an SDI line, an SDO line, a TDI line, a TDO line, a ShiftDR signal input line, an AC_Pattern_Clock or ClockDR signal input line, an UpdateDR signal input line, and a Mode signal input line. The AC boundary scan cell also includes an AC_Pattern_Source signal input line and an AC_Test signal input line. For one such embodiment, each line is coupled to receive the corresponding signal from the boundary scan logic.

Abstract: Testing AC coupled interconnects using boundary scan test methodology. Specially designed AC boundary scan cells and boundary scan logic are used. These are compatible with IEEE Standard 1149.1 testing. An AC_EXTEST method is used to determine the reliability of the AC coupled interconnections. The method includes preloading the test stimulus, initiating the AC_EXTEST instruction, executing the instruction, transferring the instruction results, and evaluating the results. During the test, the TAP controllers of both the driving and receiving ICs are held in the Run-Test/Idle state for the time required to complete execution of the instruction. During this time, the driving IC is applying the AC test stimulus to the interconnections and the receiving IC is sampling the signal. The test may be repeated with different test data and may be run together with a DC EXTEST method to determine the reliability of both the AC and the DC coupled interconnections independently.

Abstract: A boundary scan test system including a transmitter and a receiver. The system performs DC and AC boundary scan testing of the interconnections between devices. The system addresses fault masking that can occur during testing. Of concern are AC coupled interconnections while providing IEEE 1149.1 DC test compatibility. The test receiver includes an input test buffer and an interface mechanism. The input test buffer has a built-in null detection capability. The interface mechanism includes a technology mapper, one or more detectors, and an integrator. The receiver provides at least partial, if not complete, coverage for at least one of five fault syndromes that can result from single defect conditions in the system.

Abstract: Programmable test pattern driver and capture mechanisms for boundary scan cluster or functional block testing. A boundary scan test system includes at least one device under test. The device may include a Test Access Port (TAP) controller, a plurality of output AC boundary scan cells (BSCs), and a plurality of input AC BSCs. The device may further include a programmable AC_Pattern_Source signal generator configured to produce AC signal patterns that selectively remain unchanged for at least one cycle before and after an original capture cycle location, a programmable AC_Sync signal generator configured to independently control the AC_Sync signal to lead or lag an original cycle location at full cycle increments, a programmable phase controller configured to independently control either the rising or falling edge aligned AC_Pattern_Clock signal or AC_Counter_Clock signal, and an AC_Test_Clock signal switcher configured to selectively utilize one of a plurality of clock signals including a TCK signal.

Abstract: An test circuit and method for testing an integrated device having an embedded function and a built-in test circuit for testing the embedded function. The built-in test circuit provides control signals to the embedded function based upon an internal state of the built-in test circuit. The integrated device is tested by comparing the control signals provided to the embedded function to the desired control signals based upon the internal state of the built-in self test circuit to confirm the proper operation of the built-in self test circuit. The internal state of the built-in test circuit is monitored and the control signals provided to the embedded function are monitored. The monitored signals are compared to an expected signal pattern based upon the monitored internal state of the built-in test circuit. An error signal is generated if the comparison determines that the monitored control signals do not correspond to the expected signal pattern.

Abstract: A serial memory interface includes a register having a plurality of flip-flops forming a scan chain and coupled to both the input and output terminals of memory cells. An interlaced scan is established by interconnecting scan chains between multiple memory blocks. The interface structure provides a means for efficiently performing a built-in self test of an embedded memory while requiring minimal overhead in hardware structure.

Abstract: The present invention provides a test method of SOA (Single-Order Addressed) memory utilizing address data backgrounds applied to memory circuits. A memory test operation is performed using a total of (log.sub.2 N+1) address data backgrounds on an SOA memory having N mutually different addresses. Each address data background is written and read, then the inversion is written and read. Finally the address data background is again written and read for a total of 6 N(log.sub.2 N+1) operations.