Patents by Inventor Sanghyuk Hong
Sanghyuk Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11271110Abstract: Semiconductor devices and methods of fabricating the same are provided. The methods of fabricating the semiconductor devices may include providing a substrate including an active pattern protruding from the substrate, forming a first liner layer and a field isolating pattern on the substrate to cover a lower portion of the active pattern, forming a second liner layer on an upper portion of the active pattern and the field isolation pattern, and forming a dummy gate on the second liner layer.Type: GrantFiled: November 25, 2019Date of Patent: March 8, 2022Inventors: Tae-Jong Lee, Sanghyuk Hong, TaeYong Kwon, Sunjung Kim, Cheol Kim
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Patent number: 10840142Abstract: A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.Type: GrantFiled: November 7, 2018Date of Patent: November 17, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Heedon Jeong, Jae Yup Chung, Heesoo Kang, Donghyun Kim, Sanghyuk Hong, Soohun Hong
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Publication number: 20200098918Abstract: Semiconductor devices and methods of fabricating the same are provided. The methods of fabricating the semiconductor devices may include providing a substrate including an active pattern protruding from the substrate, forming a first liner layer and a field isolating pattern on the substrate to cover a lower portion of the active pattern, forming a second liner layer on an upper portion of the active pattern and the field isolation pattern, and forming a dummy gate on the second liner layer.Type: ApplicationFiled: November 25, 2019Publication date: March 26, 2020Inventors: Tae-Jong LEE, Sanghyuk HONG, TaeYong KWON, Sunjung KIM, Cheol KIM
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Patent number: 10593801Abstract: Semiconductor devices and methods of fabricating the same are provided. The methods of fabricating the semiconductor devices may include providing a substrate including an active pattern protruding from the substrate, forming a first liner layer and a field isolating pattern on the substrate to cover a lower portion of the active pattern, forming a second liner layer on an upper portion of the active pattern and the field isolation pattern, and forming a dummy gate on the second liner layer.Type: GrantFiled: March 7, 2016Date of Patent: March 17, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Jong Lee, Sanghyuk Hong, TaeYong Kwon, Sunjung Kim, Cheol Kim
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Patent number: 10411119Abstract: A method of fabricating a semiconductor device includes forming an active pattern protruding from a substrate, forming a liner layer on the active pattern, forming a sacrificial gate pattern on the liner layer and crossing the active pattern, forming source/drain regions on the active pattern and at both sides of the sacrificial gate pattern, forming an interlayer insulating layer to cover the source/drain regions, forming capping insulating patterns on the interlayer insulating layer to expose the sacrificial gate pattern, and removing the sacrificial gate pattern and the liner layer by an etching process using the capping insulating patterns as an etch mask to form a gap region exposing the active pattern. The active pattern includes a material having a lattice constant greater than a lattice constant of the substrate, and the capping insulating patterns include a material having an etch selectivity with respect to the liner layer.Type: GrantFiled: April 7, 2016Date of Patent: September 10, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hwan Lee, Sangsu Kim, Sanghyuk Hong, Seung Mo Ha
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Publication number: 20190074223Abstract: A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.Type: ApplicationFiled: November 7, 2018Publication date: March 7, 2019Inventors: Heedon JEONG, Jae Yup CHUNG, Heesoo KANG, Donghyun KIM, Sanghyuk HONG, Soohun HONG
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Patent number: 10128154Abstract: A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.Type: GrantFiled: August 10, 2017Date of Patent: November 13, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Heedon Jeong, Jae Yup Chung, Heesoo Kang, Donghyun Kim, Sanghyuk Hong, Soohun Hong
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Publication number: 20170365523Abstract: A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.Type: ApplicationFiled: August 10, 2017Publication date: December 21, 2017Inventors: Heedon JEONG, Jae Yup CHUNG, Heesoo KANG, Donghyun KIM, Sanghyuk HONG, Soohun HONG
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Patent number: 9735059Abstract: A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.Type: GrantFiled: August 19, 2015Date of Patent: August 15, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Heedon Jeong, Jae Yup Chung, Heesoo Kang, Donghyun Kim, Sanghyuk Hong, Soohun Hong
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Patent number: 9522410Abstract: A thin film deposition apparatus includes a substrate supporting unit supporting a substrate, a deposition source evaporating a deposition material to supply a steam of the deposition material to the substrate, and a deposition source shifting unit moving the deposition source so that the deposition source is relatively shifted with respect to the substrate supporting unit.Type: GrantFiled: January 18, 2013Date of Patent: December 20, 2016Assignee: Samsung Display Co., Ltd.Inventors: SukWon Jung, YongSuk Lee, SangHyuk Hong
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Publication number: 20160329414Abstract: A method of fabricating a semiconductor device includes forming an active pattern protruding from a substrate, forming a liner layer on the active pattern, forming a sacrificial gate pattern on the liner layer and crossing the active pattern, forming source/drain regions on the active pattern and at both sides of the sacrificial gate pattern, forming an interlayer insulating layer to cover the source/drain regions, forming capping insulating patterns on the interlayer insulating layer to expose the sacrificial gate pattern, and removing the sacrificial gate pattern and the liner layer by an etching process using the capping insulating patterns as an etch mask to form a gap region exposing the active pattern. The active pattern includes a material having a lattice constant greater than a lattice constant of the substrate, and the capping insulating patterns include a material having an etch selectivity with respect to the liner layer.Type: ApplicationFiled: April 7, 2016Publication date: November 10, 2016Inventors: Jae-Hwan LEE, Sangsu Kim, Sanghyuk Hong, Seung Mo Ha
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Publication number: 20160300949Abstract: Semiconductor devices and methods of fabricating the same are provided. The methods of fabricating the semiconductor devices may include providing a substrate including an active pattern protruding from the substrate, forming a first liner layer and a field isolating pattern on the substrate to cover a lower portion of the active pattern, forming a second liner layer on an upper portion of the active pattern and the field isolation pattern, and forming a dummy gate on the second liner layer.Type: ApplicationFiled: March 7, 2016Publication date: October 13, 2016Inventors: Tae-Jong LEE, Sanghyuk HONG, TaeYong KWON, Sunjung KIM, Cheol KIM
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Patent number: 9407114Abstract: Provided are a network system and a method of controlling the network system supplied with energy from an energy generation component. The network system includes an energy consumption component consuming the energy generated from the energy generation component, and driving a driving component for processing or managing a consumable. The energy consumption component is provided with one or more courses classified according to a determination factor related to the consumable. The determination factor includes a performance factor denoting a processed or managed result of the consumable. One of the courses is recommended as a driving course when the energy consumption component recognizes information about the consumable.Type: GrantFiled: May 16, 2012Date of Patent: August 2, 2016Assignee: LG ELECTRONICS INC.Inventors: Chulwoo Lee, Sangryul Lee, Joongki Min, Kwangsuk Oh, Sanghyuk Hong
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Publication number: 20150357245Abstract: A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.Type: ApplicationFiled: August 19, 2015Publication date: December 10, 2015Inventors: Heedon JEONG, Jae Yup CHUNG, Heesoo KANG, Donghyun KIM, Sanghyuk HONG, Soohun HONG
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Patent number: 9117910Abstract: A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.Type: GrantFiled: June 24, 2014Date of Patent: August 25, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Heedon Jeong, Jae Yup Chung, Heesoo Kang, Donghyun Kim, Sanghyuk Hong, Soohun Hong
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Publication number: 20140374830Abstract: A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.Type: ApplicationFiled: June 24, 2014Publication date: December 25, 2014Inventors: HEEDON JEONG, JAE YUP CHUNG, HEESOO KANG, DONGHYUN KIM, SANGHYUK HONG, SOOHUN HONG
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Publication number: 20120292997Abstract: Provided are a network system and a method of controlling the network system supplied with energy from an energy generation component. The network system includes an energy consumption component consuming the energy generated from the energy generation component, and driving a driving component for processing or managing a consumable. The energy consumption component is provided with one or more courses classified according to a determination factor related to the consumable. The determination factor includes a performance factor denoting a processed or managed result of the consumable. One of the courses is recommended as a driving course when the energy consumption component recognizes information about the consumable.Type: ApplicationFiled: May 16, 2012Publication date: November 22, 2012Inventors: Chulwoo Lee, Sangryul Lee, Joongki Min, Kwangsuk Oh, Sanghyuk Hong