Abstract: A docking control system for a vehicle and a building and a method therefor, includes a plurality of sensors including a vehicle sensor and a gate sensor, and a controller, when a vehicle approaches a gate, which controls the plurality of sensors to set amount of movement of the vehicle, to move the gate so that a vehicle door and the gate are brought into close contact with each other, and when positional satisfaction between the vehicle door and the gate is achieved, which opens the vehicle door and the gate so that an indoor space of the vehicle and an indoor space of the building are connected each other into one space.

Abstract: The inventive concept provides a teaching method for teaching a transfer position of a transfer robot. The teaching method includes: searching for an object on which a target object to be transferred by the transfer robot is placed, based on a 3D position information acquired by a first sensor; and acquiring coordinates of a second direction and coordinates of a third direction of the object based on a data acquired from a second sensor which is a different type from the first sensor.

Abstract: A vehicle body frame includes a lower frame fixed to a floor of a vehicle to define a lower region of an internal space in the vehicle, a roof frame connected to an upper portion of the lower frame to define an upper region of the internal space, configured to slid in a vertical direction of the vehicle with respect to the lower frame, to expand the internal space upwards when the roof frame slides upwards, a lower door frame forming a lower portion of a vehicle door, and an upper door frame connected to the lower door frame to form an upper portion of the vehicle door, and configured to slid together with the roof frame to expand the vehicle door upwards when the roof frame slides upwards.

Abstract: A docking system between a vehicle and a building and a control method therefor include an entrance frame configured to extend in a direction towards a vehicle door, an external door provided at a side of the vehicle door to be opened, an internal door spaced from the external door and provided at a side of the building to be opened, and a sealing unit inserted into the entrance frame to be provided between the external door and the internal door, and configured to selectively extend in the direction toward the vehicle door to connect an internal space of the vehicle and an indoor space of the building into one space.

Abstract: A service identifying and processing method using a wireless terminal message according to an exemplary embodiment of the present invention includes (a) receiving a wireless terminal message by a first entity which is a mobile device; and (b) expressing, by a first agent which is an information processing application program installed on the first entity, entity information of second entity based on the wireless terminal message and service confirmation information related to service provided by the second entity, through an application screen by the first agent.

Abstract: Disclosed herein are an apparatus and method for updating an Internet-based malware detection engine using virtual machine scaling. The method may include creating a scaling group and an update group set based on a first virtual machine image, creating a second virtual machine image for a running virtual machine in response to occurrence of a snapshot event in the virtual update group run based on the first virtual machine image, modifying the scale-out image of the scaling group to the second virtual machine image, updating the scaling group by triggering a scale-out event and a scale-in event in the scaling group in response to occurrence of an update event, and modifying the scale-in image of the scaling group to the second virtual machine image.

Abstract: The present invention relates to a cell culture scaffold, and provides a cell culture scaffold which has a hydrogel structure comprising alginate and cellulose extracted by means of algae decellularization and which enable the stable growth of cells even at low cost while having a simple preparation.

Abstract: A fuel cell stack array is disclosed. The fuel cell stack array includes a first fuel cell stack having a first upper frame structure formed with a first through-hole for exposing a first topmost connector layer positioned at top of a first single cell stack structure, a second fuel cell stack having a second upper frame structure formed with a second through-hole for exposing a second topmost connector layer positioned at top of a second single cell stack structure, and a first current collector electrically connecting the first and second topmost connector layers via the first and second through-holes.

Abstract: A fuel cell stack array is disclosed. The fuel cell stack array includes a first fuel cell stack having a first upper frame structure formed with a first through-hole for exposing a first topmost connector layer positioned at top of a first single cell stack structure, a second fuel cell stack having a second upper frame structure formed with a second through-hole for exposing a second topmost connector layer positioned at top of a second single cell stack structure, and a first current collector electrically connecting the first and second topmost connector layers via the first and second through-holes.

Abstract: A memory system includes: a first memory device including a first internal voltage generation circuit; and a second memory device including a second internal voltage generation circuit, wherein the first memory device and the second memory device receive an identical chip enable signal, and when the chip enable signal is disabled, the first internal voltage generation circuit a no the second internal voltage generation circuit are controlled in a standby mode, and when the chip enable signal is enabled, the first internal voltage generation circuit and the second internal voltage generation circuit are independently controlled to have one mode between a weak active mode and a strong active mode.

Abstract: A memory system includes: a first memory device including a first internal voltage generation circuit; and a second memory device including a second internal voltage generation circuit, wherein the first memory device and the second memory device receive an identical chip enable signal, and when the chip enable signal is disabled, the first internal voltage generation circuit and the second internal voltage generation circuit are controlled in a standby mode, and when the chip enable signal is enabled, the first internal voltage generation circuit and the second internal voltage generation circuit are independently controlled to have one mode between a weak active mode and a strong active mode.

Abstract: A memory system including a plurality of memory chips is provided. The memory system includes a first memory chip and a second memory chip that share a data bus and become active by a chip enable signal, and a controller transmitting multi chip select commands to the first and second memory chips. The first memory chip, in response to the first multichip select command, receives a first operation request transmitted by the controller through the data base, and the second memory chip, in response to the second multichip select command, receives a second operation request transmitted by the controller through the data bus before the first memory chip operates according to the first operation request.

Abstract: A memory system including a plurality of memory chips is provided. The memory system includes a first memory chip and a second memory chip that share a data bus and become active by a chip enable signal, and a controller transmitting multi chip select commands to the first and second memory chips. The first memory chip, in response to the first multichip select command, receives a first operation request transmitted by the controller through the data base, and the second memory chip, in response to the second multichip select command, receives a second operation request transmitted by the controller through the data bus before the first memory chip operates according to the first operation request.

Abstract: The present disclosure relates to a semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a ROM for storing a program algorithm, an erase algorithm, a reading algorithm, and a reset algorithm and outputting ROM data corresponding to a selected algorithm, a program counter for outputting a ROM address to the ROM so as to sequentially operate the selected algorithm, an internal circuit for performing an operation corresponding to the selected algorithm in response to a plurality of internal circuit control signals in response to the ROM data, and a reset circuit for stopping progress of a running algorithm by initializing the program counter in response to a reset command input from an outside, and performing the reset algorithm.

Abstract: A memory apparatus includes a memory cell array comprising a plurality of memory cells connected with a plurality of bit lines and a plurality of word lines, a page buffer unit connected to the plurality of bit lines and latch data read from a memory cell selected from the plurality of memory cells, and a control unit configured to generate a refresh signal according to a prestored current status and provide the refresh signal to the page buffer unit in order to substantially prevent loss of the data latched by the page buffer unit.

Abstract: The present disclosure relates to a semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a ROM for storing a program algorithm, an erase algorithm, a reading algorithm, and a reset algorithm and outputting ROM data corresponding to a selected algorithm, a program counter for outputting a ROM address to the ROM so as to sequentially operate the selected algorithm, an internal circuit for performing an operation corresponding to the selected algorithm in response to a plurality of internal circuit control signals in response to the ROM data, and a reset circuit for stopping progress of a running algorithm by initializing the program counter in response to a reset command input from an outside, and performing the reset algorithm.

Abstract: A non-volatile memory device includes: first and second planes each comprising a plurality of non-volatile memory cells; first and second buffer corresponding to the first and second planes, respectively; an input/output control unit configured to selectively control input/output paths of data stored in the first and second page buffers; a flash interface connected to the input/output control unit; and a host connected to the flash interface.

Abstract: A memory apparatus includes a memory cell array comprising a plurality of memory cells connected with a plurality of bit lines and a plurality of word lines, a page buffer unit connected to the plurality of bit lines and latch data read from a memory cell selected from the plurality of memory cells, and a control unit configured to generate a refresh signal according to a prestored current status and provide the refresh signal to the page buffer unit in order to substantially prevent loss of the data latched by the page buffer unit.

Abstract: A connector for a coaxial cable physically and electrically connects a coaxial cable with various kinds of electric members. The coaxial cable includes a hollow inner conductor and a corrugated outer conductor surrounding the inner conductor. A carrier terminal inserted into the inner conductor of the coaxial cable has a diameter elastically adjusted to an inner diameter of the inner conductor.

Abstract: A non-volatile memory device includes: first and second planes each comprising a plurality of non-volatile memory cells; first and second buffer corresponding to the first and second planes, respectively; an input/output control unit configured to selectively control input/output paths of data stored in the first and second page buffers; a flash interface connected to the input/output control unit; and a host connected to the flash interface.