Abstract: A display device includes: a first substrate, a barrier film, and a second substrate; a thin-film transistor layer, an emission material layer, an encapsulation layer and a touch detecting unit stacked on the second substrate; and a pad area in a non-display area and comprising pads connected to a driving substrate and facing the first substrate, the pads comprising: a pad contact hole formed by etching the second substrate and the barrier film; a first inorganic film and a pad electrode stacked on an inner circumferential surface of the pad contact hole; and a rear contact hole etched through a portion of the first substrate, and a pad bonded to the rear contact hole, with a middle hole connecting the pad contact hole with the rear contact hole, and the pad of the driving substrate is electrically connected to the pad electrode through a lower conductive ink.

Abstract: An anode for a secondary battery includes an anode current collector, a first anode active material layer disposed on at least one surface of the anode current collector and including a first anode active material that includes a first silicon composite oxide, and a second anode active material layer disposed on the first anode active material layer and including a second anode active material that includes a second silicon composite oxide. Each of the first silicon composite oxide and the second silicon composite oxide includes a metal. A BET specific surface area of each of the first silicon composite oxide and the second silicon composite oxide is in a range from 2.0 m2/g to 6.5 m2/g.

Abstract: According to an embodiment of the present invention, disclosed is a camera apparatus comprising: a substrate; a light emitting part; a light receiving part comprising an image sensor located on the substrate; and a controller that controls the optical part or the light source using an output value received from a photodetector, wherein the light emitting part comprises: a light source located on the substrate; a holder located on the substrate; an optical part located on the light source; a driving part that moves the optical part along an optical axis; and the photodetector located on the substrate.

Abstract: The present invention relates to a cell culture scaffold, and provides a cell culture scaffold which has a hydrogel structure comprising alginate and cellulose extracted by means of algae decellularization and which enable the stable growth of cells even at low cost while having a simple preparation.

Abstract: A fuel cell stack array is disclosed. The fuel cell stack array includes a first fuel cell stack having a first upper frame structure formed with a first through-hole for exposing a first topmost connector layer positioned at top of a first single cell stack structure, a second fuel cell stack having a second upper frame structure formed with a second through-hole for exposing a second topmost connector layer positioned at top of a second single cell stack structure, and a first current collector electrically connecting the first and second topmost connector layers via the first and second through-holes.

Abstract: A fuel cell stack array is disclosed. The fuel cell stack array includes a first fuel cell stack having a first upper frame structure formed with a first through-hole for exposing a first topmost connector layer positioned at top of a first single cell stack structure, a second fuel cell stack having a second upper frame structure formed with a second through-hole for exposing a second topmost connector layer positioned at top of a second single cell stack structure, and a first current collector electrically connecting the first and second topmost connector layers via the first and second through-holes.

Abstract: A memory system includes: a first memory device including a first internal voltage generation circuit; and a second memory device including a second internal voltage generation circuit, wherein the first memory device and the second memory device receive an identical chip enable signal, and when the chip enable signal is disabled, the first internal voltage generation circuit a no the second internal voltage generation circuit are controlled in a standby mode, and when the chip enable signal is enabled, the first internal voltage generation circuit and the second internal voltage generation circuit are independently controlled to have one mode between a weak active mode and a strong active mode.

Abstract: A memory system includes: a first memory device including a first internal voltage generation circuit; and a second memory device including a second internal voltage generation circuit, wherein the first memory device and the second memory device receive an identical chip enable signal, and when the chip enable signal is disabled, the first internal voltage generation circuit and the second internal voltage generation circuit are controlled in a standby mode, and when the chip enable signal is enabled, the first internal voltage generation circuit and the second internal voltage generation circuit are independently controlled to have one mode between a weak active mode and a strong active mode.

Abstract: A memory system including a plurality of memory chips is provided. The memory system includes a first memory chip and a second memory chip that share a data bus and become active by a chip enable signal, and a controller transmitting multi chip select commands to the first and second memory chips. The first memory chip, in response to the first multichip select command, receives a first operation request transmitted by the controller through the data base, and the second memory chip, in response to the second multichip select command, receives a second operation request transmitted by the controller through the data bus before the first memory chip operates according to the first operation request.

Abstract: A memory system including a plurality of memory chips is provided. The memory system includes a first memory chip and a second memory chip that share a data bus and become active by a chip enable signal, and a controller transmitting multi chip select commands to the first and second memory chips. The first memory chip, in response to the first multichip select command, receives a first operation request transmitted by the controller through the data base, and the second memory chip, in response to the second multichip select command, receives a second operation request transmitted by the controller through the data bus before the first memory chip operates according to the first operation request.

Abstract: The present disclosure relates to a semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a ROM for storing a program algorithm, an erase algorithm, a reading algorithm, and a reset algorithm and outputting ROM data corresponding to a selected algorithm, a program counter for outputting a ROM address to the ROM so as to sequentially operate the selected algorithm, an internal circuit for performing an operation corresponding to the selected algorithm in response to a plurality of internal circuit control signals in response to the ROM data, and a reset circuit for stopping progress of a running algorithm by initializing the program counter in response to a reset command input from an outside, and performing the reset algorithm.

Abstract: A memory apparatus includes a memory cell array comprising a plurality of memory cells connected with a plurality of bit lines and a plurality of word lines, a page buffer unit connected to the plurality of bit lines and latch data read from a memory cell selected from the plurality of memory cells, and a control unit configured to generate a refresh signal according to a prestored current status and provide the refresh signal to the page buffer unit in order to substantially prevent loss of the data latched by the page buffer unit.

Abstract: The present disclosure relates to a semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a ROM for storing a program algorithm, an erase algorithm, a reading algorithm, and a reset algorithm and outputting ROM data corresponding to a selected algorithm, a program counter for outputting a ROM address to the ROM so as to sequentially operate the selected algorithm, an internal circuit for performing an operation corresponding to the selected algorithm in response to a plurality of internal circuit control signals in response to the ROM data, and a reset circuit for stopping progress of a running algorithm by initializing the program counter in response to a reset command input from an outside, and performing the reset algorithm.

Abstract: A non-volatile memory device includes: first and second planes each comprising a plurality of non-volatile memory cells; first and second buffer corresponding to the first and second planes, respectively; an input/output control unit configured to selectively control input/output paths of data stored in the first and second page buffers; a flash interface connected to the input/output control unit; and a host connected to the flash interface.

Abstract: A memory apparatus includes a memory cell array comprising a plurality of memory cells connected with a plurality of bit lines and a plurality of word lines, a page buffer unit connected to the plurality of bit lines and latch data read from a memory cell selected from the plurality of memory cells, and a control unit configured to generate a refresh signal according to a prestored current status and provide the refresh signal to the page buffer unit in order to substantially prevent loss of the data latched by the page buffer unit.

Abstract: A connector for a coaxial cable physically and electrically connects a coaxial cable with various kinds of electric members. The coaxial cable includes a hollow inner conductor and a corrugated outer conductor surrounding the inner conductor. A carrier terminal inserted into the inner conductor of the coaxial cable has a diameter elastically adjusted to an inner diameter of the inner conductor.

Abstract: A non-volatile memory device includes: first and second planes each comprising a plurality of non-volatile memory cells; first and second buffer corresponding to the first and second planes, respectively; an input/output control unit configured to selectively control input/output paths of data stored in the first and second page buffers; a flash interface connected to the input/output control unit; and a host connected to the flash interface.

Abstract: A connector for a coaxial cable physically and electrically connects a coaxial cable with various kinds of electric members. The coaxial cable includes a hollow inner conductor and a corrugated outer conductor surrounding the inner conductor. A carrier terminal inserted into the inner conductor of the coaxial cable has a diameter elastically adjusted to an inner diameter of the inner conductor.