Abstract: A scanline driver chip includes: a chip selection de-serializer configured to provide an output enable signal based on an enable signal, a clock signal, and serial chip selection data, the serial chip selection data being received in serial order; an address data de-serializer configured to provide parallel address data based on the enable signal, the clock signal, the output enable signal, and serial address data, the serial address data being received in serial order; and a decoder-level shifter configured to provide a scanline enable signal based on the parallel address data. A display device includes: a controller configured to provide an enable signal, a clock signal, serial chip selection data, and serial address data; a plurality of the scanline driver chips each configured to provide a scanline enable signal; and a pixel array configured to be driven based on the scanline enable signal.

Abstract: A scanline driver chip includes: a chip selection de-serializer configured to provide an output enable signal based on an enable signal, a clock signal, and serial chip selection data, the serial chip selection data being received in serial order; an address data de-serializer configured to provide parallel address data based on the enable signal, the clock signal, the output enable signal, and serial address data, the serial address data being received in serial order; and a decoder-level shifter configured to provide a scanline enable signal based on the parallel address data. A display device includes: a controller configured to provide an enable signal, a clock signal, serial chip selection data, and serial address data; a plurality of the scanline driver chips each configured to provide a scanline enable signal; and a pixel array configured to be driven based on the scanline enable signal.

Abstract: A display device includes a display panel, a scan driver, a data driver, and a timing controller. The display panel includes charge-sharing control switches connected to scan lines and data lines, and each of the charge-sharing control switches is connected between adjacent data lines. The scan driver provides sequentially activated scan signals via the scan lines. The data driver provides data voltages generated by performing a digital-to-analog conversion on data signals provided via the data lines. The data driver controls the charge-sharing control switches based on one or more predetermined bits of adjacent data signals corresponding to adjacent data voltages to be applied to the adjacent data lines. The data driver controls the charge-sharing control switches in a charge-sharing period. The timing controller controls the scan driver and the data driver and provides the data signals to the data driver.

Abstract: A data driver capable of generating pre-emphasis voltages is provided. The data driver includes a pre-emphasis unit for comparing previous input data signals with current input data signals to generate pre-emphasis data signals, a first register unit for storing the current input data signals from the pre-emphasis unit and for supplying the previous input data signals to the pre-emphasis unit, and a second register unit for storing the pre-emphasis data signals.

Abstract: A level shifting device is disclosed. The device includes an input unit, a control unit, a high level generating unit, a low level generating unit and an output unit. The input unit generates a level selection signal and a plurality of output selection signals by sampling serial input data. The control unit selectively generates a high level activation signal or a low level activation signal based on the input data, and generates a switching signal based on the input data. The high level generating unit generates a high level output signal in response to the high level activation signal, and the low level generating unit generates a low level output signal in response to the low level activation signal. The output unit outputs one of the high level output signal and the low level output signal to each of a plurality of output signals in response to the switching signal.

Abstract: A level shifting device is disclosed. The device includes an input unit, a control unit, a high level generating unit, a low level generating unit and an output unit. The input unit generates a level selection signal and a plurality of output selection signals by sampling serial input data. The control unit selectively generates a high level activation signal or a low level activation signal based on the input data, and generates a switching signal based on the input data. The high level generating unit generates a high level output signal in response to the high level activation signal, and the low level generating unit generates a low level output signal in response to the low level activation signal. The output unit outputs one of the high level output signal and the low level output signal to each of a plurality of output signals in response to the switching signal.

Abstract: A data driver capable of generating pre-emphasis voltages is provided. The data driver includes a pre-emphasis unit for comparing previous input data signals with current input data signals to generate pre-emphasis data signals, a first register unit for storing the current input data signals from the pre-emphasis unit and for supplying the previous input data signals to the pre-emphasis unit, and a second register unit for storing the pre-emphasis data signals.

Abstract: In the fabrication of an integrated circuit where a porous silicon oxide layer is formed over a surface of a semiconductor substrate to electrically isolate two conductive metal layers, a via through the porous silicon oxide layer has an opening etched through the porous silicon oxide layer, a self-assembled monolayer adhering to an etched surface of the opening and to exposed pores, and a conductive material filling the opening.

Abstract: There is provided a frequency-digital signal conversion circuit for automatically converting a clock frequency into a digital signal. The frequency-digital signal conversion circuit includes: a frequency detecting unit for detecting a frequency of an input clock signal; a latch unit for sampling and latching an output of the frequency detecting unit; and a digital signal generating unit for receiving an output of the latch unit and generating a digital signal of a predetermined bits with respect to the frequency of the input clock signal.

Abstract: There is provided a frequency-digital signal conversion circuit for automatically converting a clock frequency into a digital signal. The frequency-digital signal conversion circuit includes: a frequency detecting unit for detecting a frequency of an input clock signal; a latch unit for sampling and latching an output of the frequency detecting unit; and a digital signal generating unit for receiving an output of the latch unit and generating a digital signal of a predetermined bits with respect to the frequency of the input clock signal.