Abstract: A patterning method includes etching a mask formed above a stack of two or more layers where the mask comprises a first patterned structure, a second patterned structure above the first patterned structure, where portions of the second patterned structure intersect the first patterned structure to form intersections and at least an opening. The mask includes a structure vertically between portions of the second patterned structure and the stack. The method includes etching a first layer of the stack through the opening and exposing a top surface of a second layer below the first layer, etching and removing the first patterned structure and the second patterned structure selectively to the first layer and the top surface of the second layer to form a planar mask comprising the first layer. The method further includes etching the second layer of the stack using the planar mask.

Abstract: A scanline driver chip includes: a chip selection de-serializer configured to provide an output enable signal based on an enable signal, a clock signal, and serial chip selection data, the serial chip selection data being received in serial order; an address data de-serializer configured to provide parallel address data based on the enable signal, the clock signal, the output enable signal, and serial address data, the serial address data being received in serial order; and a decoder-level shifter configured to provide a scanline enable signal based on the parallel address data. A display device includes: a controller configured to provide an enable signal, a clock signal, serial chip selection data, and serial address data; a plurality of the scanline driver chips each configured to provide a scanline enable signal; and a pixel array configured to be driven based on the scanline enable signal.

Abstract: A scanline driver chip includes: a chip selection de-serializer configured to provide an output enable signal based on an enable signal, a clock signal, and serial chip selection data, the serial chip selection data being received in serial order; an address data de-serializer configured to provide parallel address data based on the enable signal, the clock signal, the output enable signal, and serial address data, the serial address data being received in serial order; and a decoder-level shifter configured to provide a scanline enable signal based on the parallel address data. A display device includes: a controller configured to provide an enable signal, a clock signal, serial chip selection data, and serial address data; a plurality of the scanline driver chips each configured to provide a scanline enable signal; and a pixel array configured to be driven based on the scanline enable signal.

Abstract: A display device includes a display panel, a scan driver, a data driver, and a timing controller. The display panel includes charge-sharing control switches connected to scan lines and data lines, and each of the charge-sharing control switches is connected between adjacent data lines. The scan driver provides sequentially activated scan signals via the scan lines. The data driver provides data voltages generated by performing a digital-to-analog conversion on data signals provided via the data lines. The data driver controls the charge-sharing control switches based on one or more predetermined bits of adjacent data signals corresponding to adjacent data voltages to be applied to the adjacent data lines. The data driver controls the charge-sharing control switches in a charge-sharing period. The timing controller controls the scan driver and the data driver and provides the data signals to the data driver.

Abstract: A data driver capable of generating pre-emphasis voltages is provided. The data driver includes a pre-emphasis unit for comparing previous input data signals with current input data signals to generate pre-emphasis data signals, a first register unit for storing the current input data signals from the pre-emphasis unit and for supplying the previous input data signals to the pre-emphasis unit, and a second register unit for storing the pre-emphasis data signals.

Abstract: A level shifting device is disclosed. The device includes an input unit, a control unit, a high level generating unit, a low level generating unit and an output unit. The input unit generates a level selection signal and a plurality of output selection signals by sampling serial input data. The control unit selectively generates a high level activation signal or a low level activation signal based on the input data, and generates a switching signal based on the input data. The high level generating unit generates a high level output signal in response to the high level activation signal, and the low level generating unit generates a low level output signal in response to the low level activation signal. The output unit outputs one of the high level output signal and the low level output signal to each of a plurality of output signals in response to the switching signal.

Abstract: A method of forming features in a porous low-k dielectric layer disposed below a patterned organic mask is provided. Features are etched into the porous low-k dielectric layer through the patterned organic mask, and then the patterned organic mask is stripped. The stripping of the patterned organic mask includes providing a stripping gas comprising COS, forming a plasma from the stripping gas, and stopping the stripping gas. A cap layer may be provided between the porous low-k dielectric layer and the patterned organic mask. The stripping of the patterned organic mask leaves the cap layer on the porous low-k dielectric layer.

Abstract: A level shifting device is disclosed. The device includes an input unit, a control unit, a high level generating unit, a low level generating unit and an output unit. The input unit generates a level selection signal and a plurality of output selection signals by sampling serial input data. The control unit selectively generates a high level activation signal or a low level activation signal based on the input data, and generates a switching signal based on the input data. The high level generating unit generates a high level output signal in response to the high level activation signal, and the low level generating unit generates a low level output signal in response to the low level activation signal. The output unit outputs one of the high level output signal and the low level output signal to each of a plurality of output signals in response to the switching signal.

Abstract: A data driver capable of generating pre-emphasis voltages is provided. The data driver includes a pre-emphasis unit for comparing previous input data signals with current input data signals to generate pre-emphasis data signals, a first register unit for storing the current input data signals from the pre-emphasis unit and for supplying the previous input data signals to the pre-emphasis unit, and a second register unit for storing the pre-emphasis data signals.

Abstract: A method of forming dual damascene features in a porous low-k dielectric layer is provided. Vias are formed in the porous low-k dielectric layer. An organic planarization layer is formed over the porous low-k dielectric layer, wherein the organic layer fills the vias. A photoresist mask is formed over the organic planarization layer. Features are etched into the organic planarization layer comprising providing a CO2 containing etch gas and forming a plasma from the CO2 containing etch gas, which etches the organic planarization layer. Trenches are etched into the porous low-k dielectric layer using the organic planarization layer as a mask. The organic planarization layer is stripped.

Abstract: A method of forming features in a porous low-k dielectric layer disposed below a patterned organic mask is provided. Features are etched into the porous low-k dielectric layer through the patterned organic mask, and then the patterned organic mask is stripped. The stripping of the patterned organic mask includes providing a stripping gas comprising COS, forming a plasma from the stripping gas, and stopping the stripping gas. A cap layer may be provided between the porous low-k dielectric layer and the patterned organic mask. The stripping of the patterned organic mask leaves the cap layer on the porous low-k dielectric layer.

Abstract: In the fabrication of an integrated circuit where a porous silicon oxide layer is formed over a surface of a semiconductor substrate to electrically isolate two conductive metal layers, a via through the porous silicon oxide layer has an opening etched through the porous silicon oxide layer, a self-assembled monolayer adhering to an etched surface of the opening and to exposed pores, and a conductive material filling the opening.

Abstract: A method of forming dual damascene features in a porous low-k dielectric layer is provided. Vias are formed in the porous low-k dielectric layer. An organic planarization layer is formed over the porous low-k dielectric layer, wherein the organic layer fills the vias. A photoresist mask is formed over the organic planarization layer. Features are etched into the organic planarization layer comprising providing a CO2 containing etch gas and forming a plasma from the CO2 containing etch gas, which etches the organic planarization layer. Trenches are etched into the porous low-k dielectric layer using the organic planarization layer as a mask. The organic planarization layer is stripped.

Abstract: There is provided a frequency-digital signal conversion circuit for automatically converting a clock frequency into a digital signal. The frequency-digital signal conversion circuit includes: a frequency detecting unit for detecting a frequency of an input clock signal; a latch unit for sampling and latching an output of the frequency detecting unit; and a digital signal generating unit for receiving an output of the latch unit and generating a digital signal of a predetermined bits with respect to the frequency of the input clock signal.

Abstract: There is provided a frequency-digital signal conversion circuit for automatically converting a clock frequency into a digital signal. The frequency-digital signal conversion circuit includes: a frequency detecting unit for detecting a frequency of an input clock signal; a latch unit for sampling and latching an output of the frequency detecting unit; and a digital signal generating unit for receiving an output of the latch unit and generating a digital signal of a predetermined bits with respect to the frequency of the input clock signal.

Abstract: A deflection yoke for a Braun tube includes a primary 4-pole convergence yoke adapted to be positioned at a neck portion of a funnel of a Braun tube and a secondary 4-pole convergence yoke positioned in the vicinity of the funnel where horizontal and vertical deflection coils and a ferrite core are installed, for correcting a misconvergence generated due to the primary 4-pole convergence yoke, wherein at least one of the vertical and the horizontal deflection coils is wound at a first holder, and the secondary 4-pole convergence yoke is installed as an auxiliary coil wound on at least one side of the inner side or the outer side of the first holder. With this construction, occurrence of an inverse-magnetic field due to an induced magnetic field is prevented and thus a misconvergence can be easily corrected.

Abstract: A deflection yoke for a Braun tube includes a primary 4-pole convergence yoke adapted to be positioned at a neck portion of a funnel of a Braun tube and a secondary 4-pole convergence yoke positioned in the vicinity of the funnel where horizontal and vertical deflection coils and a ferrite core are installed, for correcting a misconvergence generated due to the primary 4-pole convergence yoke, wherein at least one of the vertical and the horizontal deflection coils is wound at a first holder, and the secondary 4-pole convergence yoke is installed as an auxiliary coil wound on at least one side of the inner side or the outer side of the first holder. With this construction, occurrence of an inverse-magnetic field due to an induced magnetic field is prevented and thus a misconvergence can be easily corrected.