Abstract: The present invention relates to a wave control apparatus using change of elastic modulus of thermoresponsive material, comprising: a wave modulation member having thermoresponsive material whose elastic modulus changes according to temperature variation, a wave source propagating wave through the wave modulation member, and a heating unit forming a wave modulation region by heating the wave modulation member, wherein the wave propagating through the wave modulation member from the wave source is configured to change wave characteristics when the wave passes through the wave modulation region heated by the heating unit.

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

Abstract: A semiconductor memory device including: a substrate including a cell array region and a boundary region; a first recess region at an upper portion of the substrate in the cell array region; a first bit line extending onto the boundary region and crossing the first recess region; a bit line contact in the first recess region and contacting the first bit line; a second bit line spaced apart from the first recess region and adjacent to the first bit line, the second bit line crossing the cell array region and the boundary region; a cell buried insulation pattern between a side surface of the first bit line contact and an inner wall of the first recess region; and a boundary buried insulation pattern covering sidewalls of the first bit line and the second bit line in the boundary region and including a same material as the cell buried insulation pattern.

Abstract: The present invention relates to a wave control apparatus using change of elastic modulus of thermoresponsive material, comprising: a wave modulation member having thermoresponsive material whose elastic modulus changes according to temperature variation, a wave source propagating wave through the wave modulation member, and a heating unit forming a wave modulation region by heating the wave modulation member, wherein the wave propagating through the wave modulation member from the wave source is configured to change wave characteristics when the wave passes through the wave modulation region heated by the heating unit.

Abstract: A semiconductor memory device including: a substrate including a cell array region and a boundary region; a first recess region at an upper portion of the substrate in the cell array region; a first bit line extending onto the boundary region and crossing the first recess region; a bit line contact in the first recess region and contacting the first bit line; a second bit line spaced apart from the first recess region and adjacent to the first bit line, the second bit line crossing the cell array region and the boundary region; a cell buried insulation pattern between a side surface of the first bit line contact and an inner wall of the first recess region; and a boundary buried insulation pattern covering sidewalls of the first bit line and the second bit line in the boundary region and including a same material as the cell buried insulation pattern.

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

Abstract: A flexible double-junction solar cell includes a flexible substrate including a lower electrode layer, an InGaAs solar cell disposed to be in contact with the lower electrode layer of the flexible substrate, and a GaAs solar cell disposed on the InGaAs solar cell and connected to the InGaAs solar cell in series. The GaAs solar cell includes a metal nanodisk array disposed on a lower surface thereof and a void array, aligned with the metal nanodisk array, is disposed below the metal nanodisk array.

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

Abstract: A tandem solar cell includes a substrate a plurality of sub-cells stacked on the substrate and configured to sequentially perform photoelectric conversion with different wavelength band, and a metal disk array disposed on at least one of interfaces between adjacent sub-cells. A center wavelength of wavelength bands corresponding to the sub-cells gradually decreases as progressing downward with respect to an uppermost layer. The metal disk array reflects a light transmitting a sub-cell disposed over the metal disk array without being absorbed therein. The metal disk array is inserted by means of wafer bonding.

Abstract: A flexible double-junction solar cell includes a flexible substrate including a lower electrode layer, an InGaAs solar cell disposed to be in contact with the lower electrode layer of the flexible substrate, and a GaAs solar cell disposed on the InGaAs solar cell and connected to the InGaAs solar cell in series. The GaAs solar cell includes a metal nanodisk array disposed on a lower surface thereof and a void array, aligned with the metal nanodisk array, is disposed below the metal nanodisk array.

Abstract: A tandem solar cell includes a substrate a plurality of sub-cells stacked on the substrate and configured to sequentially perform photoelectric conversion with different wavelength band, and a metal disk array disposed on at least one of interfaces between adjacent sub-cells. A center wavelength of wavelength bands corresponding to the sub-cells gradually decreases as progressing downward with respect to an uppermost layer. The metal disk array reflects a light transmitting a sub-cell disposed over the metal disk array without being absorbed therein. The metal disk array is inserted by means of wafer bonding.

Abstract: A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at least a portion of the remaining insulation layer by performing a second dry cleaning operation to form an air gap between the first and second conductive structures.

Abstract: A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at least a portion of the remaining insulation layer by performing a second dry cleaning operation to form an air gap between the first and second conductive structures.

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

Abstract: A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at

Abstract: A peripheral device management system includes a node terminal apparatus attached to a peripheral device and configured to detect an operating state of the attached peripheral device through a sensor configured to generate sensing data, and a display apparatus configured to receive the sensing data from the node terminal apparatus, to determine the operating state of the peripheral device based on the sensing data, and to display a user interface (UI) containing the operating state of the peripheral device. Accordingly, the peripheral device management system provides an Internet of things (IOT) service to a peripheral device that may not be capable of supporting an IOT service.

Abstract: Provided are a pharmaceutical composition with improved stability including palonosetron, a preparation method thereof, and a pharmaceutical package including the pharmaceutical composition.

Abstract: Provided are a pharmaceutical composition with improved stability including palonosetron, a preparation method thereof, and a pharmaceutical package including the pharmaceutical composition.

Abstract: A memory device includes a substrate including active areas and isolation areas, trenches in the isolation areas, active patterns in the active areas, the active patterns protruding from the substrate, isolation layers filling the trenches, gate trenches crossing the active patterns and the isolation layers, and gate line stacks filling the gate trenches, a first width of the gate trench in the isolation layer being greater than a second width of the gate trench in the active pattern.

Abstract: A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at