Abstract: A surface inspecting method includes: irradiating an incident light beam of a first polarized state on a target object, the incident light beam comprising parallel light and having a cross-sectional area: measuring a second polarized state of a reflected light beam reflected from the target object; and performing inspection on an entire area of the target object on which the incident light beam is irradiated, based on a variation between the first polarized state and the second polarized state.

Abstract: A test device includes a test unit and a voltage selection circuit. The test unit is configured to detect a voltage at a test pad of a semiconductor device under test by applying a test current to the test pad. The voltage selection circuit is configured to apply a selection voltage to a ground pad of the semiconductor device under test by selecting one of a plurality of voltages according to a test mode.

Abstract: A surface inspecting method includes: irradiating an incident light beam of a first polarized state on a target object, the incident light beam comprising parallel light and having a cross-sectional area: measuring a second polarized state of a reflected light beam reflected from the target object; and performing inspection on an entire area of the target object on which the incident light beam is irradiated, based on a variation between the first polarized state and the second polarized state.

Abstract: A test device includes a test unit and a voltage selection circuit. The test unit is configured to detect a voltage at a test pad of a semiconductor device under test by applying a test current to the test pad. The voltage selection circuit is configured to apply a selection voltage to a ground pad of the semiconductor device under test by selecting one of a plurality of voltages according to a test mode.

Abstract: A method of testing a semiconductor memory includes generating a logical value of a test pattern through an algorithm pattern generator included in a field programmable gate array. The generated logical value is programmed in a DUT under the control of a DQ signal responding to a DQ enable signal that is generated from automatic test equipment and is then transferred to the field programmable gate array. The programmed logical value is captured from the DUT under the control the DQ signal. The generated logical value is compared with the captured logical value. Whether the DUT is defective is determined according to a result of the comparison. The DQ enable signal is applied to a time point different from a time point when a SYNC clock for synchronizing the automatic test equipment with the field programmable gate array is applied.

Abstract: A semiconductor device, which is mounted on a device interface board to interface an electrical measuring signal between automated test equipment (ATE) and a device under test (DUT), includes an AC test unit, a DC test unit, a first input/output (I/O) interface unit, and a second I/O interface unit. The AC test unit tests an AC characteristic of the DUT. The DC test unit provides a DC test path according to attributes of I/O terminals of the DUT. The first I/O interface unit selectively connects the AC test unit or the DC test unit to the ATE in response to a mode control signal. The second I/O interface unit selectively connects the AC test unit or the DC test unit to the DUT in response to the mode control signal.

Abstract: A test interface board comprises at least one switch matrix including a plurality of switching elements that connect a plurality of connection nodes to each other. The at least one switch matrix is configured to connect a plurality of channels of an automatic test equipment (ATE) to respective pin positions corresponding to a device under test (DUT) in response to switching control signals. The plurality of channels provide test operation signals for testing the DUT. A control logic is configured to generate the switching control signals based on pin configuration information of the DUT.