Abstract: A filtering device for passing a frequency component above a first cutoff frequency in an input signal includes an amplification circuit configured to generate an amplification signal based on the input signal, a first feedback signal, and a second feedback signal, a filter circuit configured to generate an output signal by passing a frequency component above a second cutoff frequency higher than the first cutoff frequency in the amplification signal, and a feedback circuit configured to generate the first feedback signal and the second feedback signal by amplifying the output signal, the filter circuit configured to set the first cutoff frequency based on a first amplification value corresponding to a gain of the amplification circuit and the second cutoff frequency.

Abstract: A signal processor includes a first filter circuit configured to generate an output signal based on an input signal and a feedback signal, the first filter circuit including a first resistor and a first capacitor, a filtering frequency range of the signal processor being set based on a first resistance of the first resistor and a first capacitance of the first capacitor, a second filter circuit connected to a feedback path of the first filter circuit, the second filter circuit being configured to generate an intermediate signal based on the output signal, and an offset cancellation circuit connected to the feedback path of the first filter circuit, the offset cancellation circuit being configured to generate the feedback signal based on the intermediate signal.

Abstract: A system and a method for loop exit are disclosed. A unit scheduler includes a command queue, a report queue, an interface, and a unit controller. The command queue is configured to store commands for execution in an iterative procedure for an application using a transformer model with a multi-head attention (MHA) mechanism and a decoder. The report queue is configured to store status reports on the execution of the commands. The interface is configured to communicate with a host processor to receive the commands and to transmit the status reports. The unit controller is configured to determine a change of the iterative procedure based on a loop exit condition being met. The unit controller reports the loop exit condition in the report queue.

Abstract: A processor is disclosed. A first processing layer of the processor may process a first vector into a second vector. A second processing layer may process the second vector into a third vector. A comparator to determine a similarity of the third vector and a fourth vector. A refine module may refine the third vector into a fifth vector based at least in part on the similarity of the third vector and the fourth vector.

Abstract: A device configured to perform second order intercept point (IP2) calibration for a wireless transceiver includes a memory storing instructions, an interface, and at least one processor communicatively coupled to the interface and to the memory. The interface is configured to receive, from the wireless transceiver, a signal including second order intermodulation distortion (IMD2), and transmit, to the wireless transceiver, an in-phase correction code (I-correction code) and a quadrature-phase correction code (Q-correction code). The at least one processor is configured to execute the instructions to analyze a level of the IMD2 based on a plurality of heterogeneous methods, and adjust at least one of the I-correction code or the Q-correction code based on analysis results.

Abstract: A combiner includes a first unit combiner including a first primary winding connected to a first input terminal, a second primary winding connected to a second input terminal, and a first secondary winding having first and second end portions, the first end portion connected to an output terminal, wherein the first primary winding, the second primary winding, and the first secondary winding are stacked and form a first loop, a second unit combiner including a third primary winding connected to a third input terminal, a fourth primary winding connected to a fourth input terminal, and a second secondary winding having third and fourth end portions, the third end portion connected to the output terminal, wherein the third primary winding, the fourth primary winding, and the second secondary winding are stacked and form a second loop, and a third secondary winding connected between the first and fourth end portions.

Abstract: A phase-locked loop (PLL) circuit comprising an oscillator including a first and a second capacitor cell array, each including a plurality of capacitor cells, and a control logic circuit connected to the oscillator. The control logic circuit configured to generate control code configured to control the oscillator such that the oscillator is configured to output a signal with a target frequency, the control code generated based on a first frequency of a first signal output from the oscillator and the target frequency, control at least some of capacitor cells included in the first capacitor cell array based on a first partial code generated based on a specified number of bits of the control code, and control at least some of capacitor cells included in the second capacitor cell array based on a second partial code generated based on bits other than the specified number of bits of the control code.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an active pattern, a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction, a separation structure crossing the active pattern and extending in the first direction, a first gate dielectric pattern disposed on a side surface of the gate electrode, a second gate dielectric pattern disposed on a side surface of the separation structure, and a gate capping pattern covering a top surface of the gate electrode. A level of a top surface of the separation structure is higher than a level of a top surface of the gate capping pattern.

Abstract: An electronic circuit includes a first inductor connected to an input terminal, a second inductor and a third inductor connected in series to each other and connected in parallel with the first inductor, a first switch connected between the second inductor and the third inductor, and a processor electrically connected to the first switch. The processor may be configured to close the first switch in response to a first request such that a first signal in a first frequency band is output through an output side of the electronic circuit, and to open the first switch in response to a second request, distinct from the first request, such that a second signal in a second frequency band, lower than the first frequency band, is output through the output side.

Abstract: A unit amplification circuit includes a push-pull circuit having a transistor with a gate connected to an input terminal, a symmetrical circuit connected symmetrically to the push-pull circuit and configured to be turned off in a first operation mode and turned on in a second operation mode, and a path control circuit connected to a drain of the transistor and configured to connect the drain and an output terminal in the first operation mode and to disconnect the drain and the output terminal in the second operation mode.

Abstract: An RF circuit including: first and second ports receiving first and second RF signals; a (1-1)-th amplification stage and a (1-2)-th amplification stage connected to the first port and a first ground to amplify the first RF signal; a (2-1)-th amplification stage and a (2-2)-th amplification stage connected to the second port and a second ground to amplify the second RF signal; a (1-1)-th switch connected to the (1-1)-th amplification stage and the second ground, and a (1-2)-th switch connected to the (1-2)-th amplification stage and the second ground; a (2-1)-th switch connected to the (2-1)-th amplification stage and the first ground, and a (2-2)-th switch connected to the (2-2)-th amplification stage and the first ground; and a mixer to mix the first RF signal or the second RF signal with an LO signal, and mix the first RF signal or the second RF signal with the LO signal.

Abstract: A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator configured to generate an output clock signal of the PLL circuit, a phase detector configured to generate a phase error signal representing a phase difference between a first clock signal based on a reference clock signal and a second clock signal based on the output clock signal, a comparator configured to generate a phase error sign signal based on a reference voltage and the phase error signal, and a reference voltage generation circuit configured to scale first and second sign values of the phase error sign signal based on a fixed gain value and a variable gain value, respectively, and generate the reference voltage based on the scaled first and second sign values.

Abstract: A switchable coil includes a first coil including a first outer coil and a first inner coil, the first inner coil and the first outer coil forming a first crossing-region, a second coil including a second outer coil and a second inner coil, the second inner coil and the second outer coil forming a second crossing-region, and the second crossing-region being inside the first inner coil viewed in a first direction, and a switch connected to a region facing the second crossing-region in the second inner coil.

Abstract: An electronic device includes an amplifier circuit configured to amplify a radio frequency (RF) signal received from an antenna, the RF signal having a receiving power, an attenuator circuit connected between the amplifier circuit and a mixer, the attenuator circuit including at least one resistor and at least one transistor, and a processor configured to turn on a first transistor among the at least one transistor based on the receiving power being less than a threshold value, a signal output from the amplifier circuit being directly transferred to the mixer based on the first transistor being turned on, and control one or more transistors among the at least one transistor using a look-up table based on the receiving power being greater than or equal to the threshold value, the attenuator circuit having a resistance value corresponding to the receiving power based on the control of the one or more transistors.

Abstract: Disclosed is a transmitter. The transmitter includes a plurality of power amplifiers, each of the plurality of power amplifiers being configured to receive an RF input signal, a parallel power combiner configured to combine outputs of the plurality of power amplifiers to generate an RF output signal, a supply voltage switch configured to provide one supply voltage to the plurality of power amplifiers, the one supply voltage being selected from among a plurality of supply voltages of different voltage levels, and a controller configured to control an output power of the RF output signal by selecting the one supply voltage from among the plurality of supply voltages, and controlling whether to activate each of the plurality of power amplifiers.

Abstract: A multi-stack power amplifier having a differential structure includes a first stack including a first amplifier element, configured to amplify a first signal having a first phase, and a second amplifier element configured to amplify a second signal having a second phase opposite to the first phase; and a second stack including a third amplifier element, connected to an output terminal of the first amplifier element through a first interconnection, and a fourth amplifier element connected to an output terminal of the second amplifier element through a second interconnection intersecting the first interconnection.

Abstract: Disclosed is an RF circuit, which includes a mixer that converts a first signal into a second signal using a local oscillator (LO) signal, an amplifier that amplifies the second signal, and an impedance tuner circuit connected between the mixer and an input terminal of the amplifier, and that adjusts a conversion gain of the mixer by presenting a variable impedance.

Abstract: A transceiver includes a phase shifter configured to adjust phase of a receive signal input at a first node of the phase shifter to provide an output receive signal output from a second node of the phase shifter in a receive mode, and to adjust phase of a transmit signal input at the first node to provide an output transmit signal at the second node in a transmit mode.

Abstract: Disclosed is an amplifier including a first transistor and a second transistor to which differential input signals are applied to gate terminals thereof, respectively, a second transistor having a first end connected to the first transistor, a gate terminal receiving a first bias signal, and a second end outputting a first differential output signal of a differential output signal pair, a fourth transistor having a first end connected to the second transistor, a gate terminal receiving a second bias signal, and having a second end outputting the a second differential output signal, and a pair of capacitors coupled to the second transistor and the fourth transistor, and having a cross-coupled structure with respect to each other.

Abstract: A radio-frequency (RF) chip includes a mixer configured to mix a local oscillation signal with a baseband signal to output an RF signal, an amplification stage configured to amplify the RF signal through a plurality of unit amplifiers operating in response to a first control signal, and a compensation capacitor bank provided between the mixer and the amplification stage. The compensation capacitor bank is configured to adjust a capacitance of the compensation capacitor bank based on a second control signal, the second control signal being complementary to the first control signal.