Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cell layouts in semiconductor structures and methods of manufacture. A structure includes: a plurality of abutting cells each of which include transistors with gate structures having diffusion regions; a contact spanning across abutting cells of the plurality of abutting cells and contacting to the diffusion regions of separate cells of the abutting cells; and a continuous active region spanning across the plurality of abutting cells, wherein the continuous active region includes a drain-source abutment with L-shape construct, a source-source abutment with U-shape construct, and a drain-drain abutment with a filler cell located between a drain-drain abutment.

Abstract: Dual port static random access memory (SRAM) bitcell structures with improve symmetry in access transistors physical placement are provided. The bitcell structures may include, for example, two pairs of parallel pull-down transistors. The bitcell structures may also include pass-gate transistors PGLA and PGRA forming a first port, and pass-gate transistors PGLB and PGRB forming a second port. The pass-gate transistors PGLA and PGLB may be adjacent one another and a first side of the bitcell structure, and pass-gate transistors PGRA and PGRB may be adjacent one another and a second side of the bitcell structure. Each of the pass-gate transistors PGLA and PGLB may be connected with one of the pull-down transistors of one of the pairs of parallel pull-down transistors. Similarly, each of the pass-gate transistors PGRA and PGRB may be connected with one of the pull-down transistors of the other pair of parallel pull-down transistors.

Abstract: Dual port static random access memory (SRAM) bitcell structures with improve symmetry in access transistors physical placement are provided. The bitcell structures may include, for example, two pairs of parallel pull-down transistors. The bitcell structures may also include pass-gate transistors PGLA and PGRA forming a first port, and pass-gate transistors PGLB and PGRB forming a second port. The pass-gate transistors PGLA and PGLB may be adjacent one another and a first side of the bitcell structure, and pass-gate transistors PGRA and PGRB may be adjacent one another and a second side of the bitcell structure. Each of the pass-gate transistors PGLA and PGLB may be connected with one of the pull-down transistors of one of the pairs of parallel pull-down transistors. Similarly, each of the pass-gate transistors PGRA and PGRB may be connected with one of the pull-down transistors of the other pair of parallel pull-down transistors.