Abstract: Disclosed is a stateful logic-in-memory using silicon diodes. More particularly, the stateful logic-in-memory according to an embodiment of the present invention includes a plurality of silicon diodes, each of the silicon diodes includes an anode region, a first channel region, a second channel region and a cathode region and is included as a memory cell.

Abstract: Disclosed is an oscillatory neural network circuitry using oscillators including a gated diode. An oscillatory neural network circuitry according to an embodiment of the present disclosure using oscillators including a gated diode can represent at least two graph colors of an input graph based on phase differences in output voltages over time, as phase differences occur in the output voltages depending on time differences of input voltages applied to at least two gated diodes constituting at least two oscillators.

Abstract: Disclosed is a gated diode-based true random number generator capable of encrypting information. More particularly, a gated diode-based true random number generator according to an embodiment of the present disclosure includes a gated diode where a p+-i-n+ diode structure is positioned between a drain terminal and a source terminal, a gate-insulating film is positioned on an intrinsic region of the p+-i-n+ diode structure, and two gate terminals are positioned on the gate-insulating film; and a control transistor where a control drain terminal is connected to the source terminal, wherein the control gate terminal and the control source terminal are constituted together with the control drain terminal, and the control transistor controls electron injection into the p+-i-n+ diode structure according to control of a gate voltage VMOS applied through the control gate terminal.

Abstract: The feedback field-effect transistor-based ring oscillator includes a plurality of feedback field-effect transistors each in which a diode structure is present as an n-type doped channel region and a p-type doped channel region between a drain terminal and a source terminal, a gate terminal is present in the diode structure, wherein the plurality of feedback field-effect transistors operates as p-channel mode when the gate terminal is present on the n-type doped channel region and operates as n-channnel mode when the gate terminal is present on the p-type doped channel region, and in a plurality of inverters formed by the plurality of feedback field-effect transistor, an output terminal of an inverter of each stage is input to an input terminal of a next stage and an oscillation operation is performed based on supply voltage applied through the drain terminal and the source terminal.

Abstract: The feedback field-effect transistor-based ring oscillator includes a plurality of feedback field-effect transistors each in which a diode structure is present as an n-type doped channel region and a p-type doped channel region between a drain terminal and a source terminal, a gate terminal is present in the diode structure, wherein the plurality of feedback field-effect transistors operates as p-channel mode when the gate terminal is present on the n-type doped channel region and operates as n-channel mode when the gate terminal is present on the p-type doped channel region, and in a plurality of inverters formed by the plurality of feedback field-effect transistor, an output terminal of an inverter of each stage is input to an input terminal of a next stage and an oscillation operation is performed based on supply voltage applied through the drain terminal and the source terminal.

Abstract: Disclosed is a binarized neural network circuitry using a quasi-nonvolatile memory device.

Abstract: The present invention relates to a reconfigurable logic-in-memory cell consisting of triple-gate feedback memory elements. The reconfigurable logic-in-memory cell according to one embodiment of the present invention includes a plurality of triple-gate feedback memory elements including a drain region, a channel region, a source region, and a gate region where first and second programming gate electrodes and a control gate electrode are formed on the channel region.

Abstract: The present disclosure relates to a universal logic memory block using a plurality of universal logic memory cells. The universal logic memory block according to one embodiment of the present disclosure may implement various combinational logical operations in a single structure by combining logical operation results from a plurality of universal logic memory cells using triple-gate silicon devices driven by a positive feedback loop.

Abstract: The present disclosure relates to a universal logic memory cell composed of triple-gate silicon devices. The universal logic memory cell according to one embodiment of the present disclosure may perform a ternary logic operation function and a memory function using triple-gate silicon devices driven by a positive feedback loop.

Abstract: The present disclosure relates to a binarized neural network circuitry using silicon-gated diodes. The binarized neural network circuitry according to one embodiment of the present disclosure includes a plurality of silicon-gated diodes in which a diode structure as a channel area is located between an anode terminal and a cathode terminal, a gate terminal is located on the diode structure to implement unidirectional switching through potential barrier control in the channel area based on different voltages applied to each of the anode terminal and the gate terminal, and memory characteristics are realized as holes or electrons accumulate in the potential well due to a positive feedback loop.

Abstract: Disclosed is a stateful logic-in-memory using silicon diodes. More particularly, the stateful logic-in-memory according to an embodiment of the present invention includes a plurality of silicon diodes, each of the silicon diodes includes an anode region, a first channel region, a second channel region and a cathode region and is included as a memory cell.

Abstract: A transistor is disclosed that includes an active layer and a gate electrode. The active layer includes a first conductor layer including metal atoms, a layer of semiconductor material disposed above the first conductor layer, and a second conductor layer disposed above the semiconductor material layer and including the metal atoms. The gate electrode overlaps a part of the active layer and is electrically insulated from the active layer.

Abstract: The present disclosure relates to a novel integrate-and-fire (IF) neuron circuit using a single-gated feedback field-effect transistor (FBFET) to realize small size and low power consumption. According to the present disclosure, the neuron circuit according to one embodiment may generate potential by charging current input from synapses through a capacitor. In this case, when the generated potential exceeds a threshold value, the neuron circuit may generate and output a spike voltage corresponding to the generated potential using a single-gated feedback field-effect transistor connected to the capacitor. Then, the neuron circuit may reset the generated spike voltage using transistors connected to the feedback field-effect transistor.

Abstract: The present disclosure relates to an energy harvesting technology for generating electrical energy by using a combination of a solar cell and a thermoelectric device. An energy harvesting system according to one embodiment of the present disclosure may include a solar cell for generating electrical energy based on sunlight; a heat transfer layer formed on at least one edge portion of the upper surface of the solar cell on which sunlight is incident; and a thermoelectric device including a first electrode, a second electrode, a thermoelectric channel disposed between the first and second electrodes, having a horizontal structure in which the first electrode is disposed on the heat transfer layer to be arranged horizontally with respect to the solar cell, and configured to generate additional electrical energy based on the temperature difference between the first and second electrodes.

Abstract: Disclosed is technology that is driven using a positive feedback loop of a feedback field-effect transistor and is capable of performing a logic-in memory function. The logic-in-memory inverter includes a metal oxide semiconductor field-effect transistor, and a feedback field-effect transistor in which a drain region of a nanostructure is connected in series to a drain region of the metal oxide semiconductor field-effect transistor, wherein the logic-in-memory inverter performs a logical operation is performed based on an output voltage VOUT that changes depending on a level of an input voltage VIN that is input to a gate electrode of the feedback field-effect transistor and a gate electrode of the metal oxide semiconductor field-effect transistor while a source voltage VSS is input to a source region of the nanostructure and a drain voltage VDD is input to a source region of the metal oxide semiconductor field-effect transistor.

Abstract: The present disclosure relates to an energy harvesting system for generating electrical energy by using a solar cell and a thermoelectric device. The energy harvesting system according to one embodiment of the present disclosure may include a solar cell for generating electrical energy based on sunlight; an interface layer located under the solar cell and including a heat transfer layer for transferring heat generated by the solar cell; a thermoelectric device located under the interface layer, including a first electrode, a second electrode, and a thermoelectric channel located between the first and second electrodes, and configured to generate electrical energy based on a temperature difference between the first and second electrodes that occurs when heat generated by the solar cell is transferred to the first electrode through the heat transfer layer; and a cooling layer located under the thermoelectric device and cooling the second electrode to increase the temperature difference.

Abstract: The present disclosure relates to an integrated dual-sided all-in-one energy system including a plurality of vertically stacked dual-sided all-in-one energy apparatuses, each including an energy-harvesting device and an energy-storage device disposed on both sides of a substrate, and according to one embodiment of the present disclosure, an integrated dual-sided all-in-one energy system may include a plurality of dual-sided all-in-one energy apparatuses, each including an energy-harvesting device that is formed as an electrode pattern on one side of a substrate and generates electrical energy by harvesting energy based on a temperature difference between a first side and a second side and an energy-storage device that is formed on the other side of the substrate and is selectively connected to the energy-harvesting device based on the electrode pattern to store the generated electrical energy.

Abstract: Disclosed is technology that is driven using a positive feedback loop of a feedback field-effect transistor and is capable of performing a logic-in memory function. The logic-in-memory inverter includes a metal oxide semiconductor field-effect transistor, and a feedback field-effect transistor in which a drain region of a nanostructure is connected in series to a drain region of the metal oxide semiconductor field-effect transistor, wherein the logic-in-memory inverter performs a logical operation is performed based on an output voltage VOUT that changes depending on a level of an input voltage VIN that is input to a gate electrode of the feedback field-effect transistor and a gate electrode of the metal oxide semiconductor field-effect transistor while a source voltage VSS is input to a source region of the nanostructure and a drain voltage VDD is input to a source region of the metal oxide semiconductor field-effect transistor.

Abstract: The present disclosure relates to an energy harvesting technology for generating electrical energy by using a combination of a solar cell and a thermoelectric device. An energy harvesting system according to one embodiment of the present disclosure may include a solar cell for generating electrical energy based on sunlight; a heat transfer layer formed on at least one edge portion of the upper surface of the solar cell on which sunlight is incident; and a thermoelectric device including a first electrode, a second electrode, a thermoelectric channel disposed between the first and second electrodes, having a horizontal structure in which the first electrode is disposed on the heat transfer layer to be arranged horizontally with respect to the solar cell, and configured to generate additional electrical energy based on the temperature difference between the first and second electrodes.

Abstract: The present disclosure relates to a novel neuron circuit using a p-n-p-n diode to realize small size and low power consumption. The neuron circuit according to one embodiment of the present disclosure may generate potential by charging current input from synapses through a capacitor. In this case, when the generated potential exceeds a critical value, the neuron circuit may generate and output a spike voltage corresponding to the generated potential using a p-n-p-n diode connected to the capacitor.