Abstract: A memory system includes a nonvolatile memory device and a controller. The nonvolatile memory device includes a memory block including a plurality of memory cells, a first memory region of memory cells coupled to a first word line and a second memory region of memory cells coupled to a second word line. The controller performs a single level cell (SLC) program operation on the second memory region and perform a fine program operation on the first memory region after a completion of the SLC program operation on the second memory region.

Abstract: A memory system including a storage device comprising a plurality of memory blocks comprising a plurality of pages; and a memory controller configured to update and maintain a page address that is included in a weak page table, based on a number of fail bits for each page that has been accessed based on a page address on which a normal read operation has been indicated, and configured to perform a maintenance operation on the storage device every preset cycle based on the weak page table.

Abstract: Disclosed is an anti-buckling jig of a fracture toughness test. The anti-buckling jig includes: a first jig unit provided in a form of surrounding one side surface of a specimen; a second jig unit provided in a form of surrounding the other side surface of the specimen; and a screw provided to allow the first jig unit and the second jig unit to be coupled to each other. During the fracture toughness test of the specimen, the first jig unit and the second jig unit simultaneously support both sides of the specimen, so that the specimen is cracked in a single direction.

Abstract: A memory system includes a nonvolatile memory device and a controller. The nonvolatile memory device includes a memory block including a plurality of memory cells, a first memory region of memory cells coupled to a first word line and a second memory region of memory cells coupled to a second word line. The controller performs a single level cell (SLC) program operation on the second memory region and perform a fine program operation on the first memory region after a completion of the SLC program operation on the second memory region.

Abstract: A memory system includes a memory device including a plane including a plurality of memory blocks for storing multi-bit data; and a controller configured to detect, when a problem-causing operation is performed on a first memory block among the memory blocks, remaining memory blocks, except the first memory block, in the plane as being in a problem occurrence candidate group, search for a table, when a read command for a second memory block of the problem occurrence candidate group is received, for a read voltage application order corresponding to the second memory block, and control the memory device to perform a read operation on the second memory block by sequentially applying a plurality of read voltages according to the searched read voltage application order, wherein the problem-causing operation is a program operation or an erase operation.

Abstract: A memory device may include: a control circuit comprising a first verification component suitable for counting the number of memory cells in the selected word line having an excessively high threshold voltage as excessive memory cells, after a program operation is completed; and a second verification component suitable for counting the number of failed bits when the number of excessive memory cells counted is greater than or equal to an excess threshold value, and suitable for outputting a pass or fail signal for the program operation according to the count of at least one of the first verification component and the second verification component.

Abstract: Disclosed is an anti-buckling jig of a fracture toughness test. The anti-buckling jig includes: a first jig unit provided in a form of surrounding one side surface of a specimen; a second jig unit provided in a form of surrounding the other side surface of the specimen; and a screw provided to allow the first jig unit and the second jig unit to be coupled to each other. During the fracture toughness test of the specimen, the first jig unit and the second jig unit simultaneously support both sides of the specimen, so that the specimen is cracked in a single direction.

Abstract: A memory system includes a memory device including a plane including a plurality of memory blocks for storing multi-bit data; and a controller configured to detect, when a problem-causing operation is performed on a first memory block among the memory blocks, remaining memory blocks, except the first memory block, in the plane as being in a problem occurrence candidate group, search for a table, when a read command for a second memory block of the problem occurrence candidate group is received, for a read voltage application order corresponding to the second memory block, and control the memory device to perform a read operation on the second memory block by sequentially applying a plurality of read voltages according to the searched read voltage application order, wherein the problem-causing operation is a program operation or an erase operation.

Abstract: A memory controller configured to control a memory device including memory cells includes an input/output buffer configured to store input data provided from a host; a data converter configured to generate program data obtained by converting the input data such that the number of specific data patterns among data patterns to be stored in the memory cells is changed; and an operation controller configured to provide the program data to the memory device. The program data is generated by selectively inverting a plurality of pieces of logical page data included in the input data.

Abstract: A memory device may include: a control circuit comprising a first verification component suitable for counting the number of memory cells in the selected word line having an excessively high threshold voltage as excessive memory cells, after a program operation is completed; and a second verification component suitable for counting the number of failed bits when the number of excessive memory cells counted is greater than or equal to an excess threshold value, and suitable for outputting a pass or fail signal for the program operation according to the count of at least one of the first verification component and the second verification component.

Abstract: A memory device may include: a control circuit comprising a first verification component suitable for counting the number of memory cells in the selected word line having an excessively high threshold voltage as excessive memory cells, after a program operation is completed; and a second verification component suitable for counting the number of failed bits when the number of excessive memory cells counted is greater than or equal to an excess threshold value, and suitable for outputting a pass or fail signal for the program operation according to the count of at least one of the first verification component and the second verification component.

Abstract: A memory controller configured to control a memory device including memory cells includes an input/output buffer configured to store input data provided from a host; a data converter configured to generate program data obtained by converting the input data such that the number of specific data patterns among data patterns to be stored in the memory cells is changed; and an operation controller configured to provide the program data to the memory device. The program data is generated by selectively inverting a plurality of pieces of logical page data included in the input data.

Abstract: Provided herein is a semiconductor memory device exhibiting improved operating speed and a method of operating the semiconductor memory device. The semiconductor memory device may include a memory cell array, a peripheral circuit, and a control logic. The memory cell array may include a plurality of memory blocks. The peripheral circuit may perform a read operation on the memory cell array. The control logic may control an operation of the peripheral circuit. The control logic may control the peripheral circuit to perform a repair column masking operation on a selected memory block of the plurality of memory blocks, perform a first test operation on first drain select transistors included in the selected memory block, perform the first test operation on second drain select transistors different from the first drain select transistors while a result of the repair column masking operation remains.

Abstract: An image sensor includes: a pixel array where a plurality of pixel groups are arrayed in two dimensions, wherein each of the plurality of the pixel groups includes: a first pixel suitable for sensing a first color signal that is color-separated through a first color filter; and a second pixel suitable for sensing a second color signal that is color-separated through a second color filter and has a longer wavelength than the first color signal, and a volume of a first color filter or a second color filter that is positioned in a peripheral area of the pixel array is different from a volume of a first color filter or a second color filter that is positioned in a central area of the pixel array.

Abstract: Disclosed are an unmanned aerial vehicle and an automatic charging device for the aerial vehicle. The aerial vehicle includes a main body comprising a battery and a flying power providing unit driven by power supplied from the battery to generate flying power; and a connecting portion comprising a first charging terminal and a second charging terminal disposed in the main body and electrically connected to different polarities, respectively of the battery. The charging device includes a charging platform in which the aerial vehicle is seated; a first electrode and a second electrode spaced apart from each other in the charging platform; and a power supply unit electrically connected to the first electrode and the second electrode.

Abstract: A memory device may include: a control circuit comprising a first verification component suitable for counting the number of memory cells in the selected word line having an excessively high threshold voltage as excessive memory cells, after a program operation is completed; and a second verification component suitable for counting the number of failed bits when the number of excessive memory cells counted is greater than or equal to an excess threshold value, and suitable for outputting a pass or fail signal for the program operation according to the count of at least one of the first verification component and the second verification component.

Abstract: A system and method for transferring content among multiple devices are disclosed. Herein, the system for transferring content may include a coupling controller configured to identify a user equipment in accordance with a content transfer request and to perform coupling with the identified user equipment, and a content transfer unit configured to transmit content to the user equipment or to receive content from the user equipment, when coupling is completed.

Abstract: A curved image sensor includes: a supporting substrate; an image sensor chip formed over the supporting substrate and including a curved light incidence surface; and a flare ghost preventive film formed over the curved light incidence surface and including a planar upper surface.

Abstract: A dual ignition structure for a thermal battery includes a header assembly positioned at an upper part of the thermal battery and including a contact terminal, an upper igniter connected to the contact terminal of the header assembly, an upper assembly supporting the upper igniter; a lower igniter positioned at a lower part of the thermal battery and coupled to the upper igniter in a symmetrical manner, a lower assembly supporting the lower igniter; and a nickel current collector connecting the upper igniter and the lower igniter.

Abstract: Provided herein is a semiconductor memory device exhibiting improved operating speed and a method of operating the semiconductor memory device. The semiconductor memory device may include a memory cell array, a peripheral circuit, and a control logic. The memory cell array may include a plurality of memory blocks. The peripheral circuit may perform a read operation on the memory cell array. The control logic may control an operation of the peripheral circuit. The control logic may control the peripheral circuit to perform a repair column masking operation on a selected memory block of the plurality of memory blocks, perform a first test operation on first drain select transistors included in the selected memory block, perform the first test operation on second drain select transistors different from the first drain select transistors while a result of the repair column masking operation remains.