Abstract: A vehicle seat reinforcement device includes a leg portion mounted on a floor panel, a seat cushion frame slidably mounted on the leg portion, and a load reinforcing structure connected between the leg portion and the seat cushion frame, wherein when a seat belt anchorage load is transferred to the seat cushion frame, the seat cushion frame is locked to the leg portion by the load reinforcing structure.

Abstract: A semiconductor device is provided. The semiconductor device comprises a first memory unit including a first memory area, and a first logic area electrically connected to the first memory area, the first logic area including a cache memory and an interface port. The first memory unit executes a data transmission and reception operation with a memory unit adjacent to the first memory unit via the first interface port and the cache memory.

Abstract: A semiconductor device is provided. The semiconductor device comprises a first memory unit including a first memory area, and a first logic area electrically connected to the first memory area, the first logic area including a cache memory and an interface port. The first memory unit executes a data transmission and reception operation with a memory unit adjacent to the first memory unit via the first interface port and the cache memory.

Abstract: A semiconductor device is provided. The semiconductor device comprises a first memory unit including a first memory area, and a first logic area electrically connected to the first memory area, the first logic area including a cache memory and an interface port. The first memory unit executes a data transmission and reception operation with a memory unit adjacent to the first memory unit via the first interface port and the cache memory.

Abstract: A local oscillator generator (LO generator) may be configured to transmit an LO signal to a mixer. The LO generator may include an input buffer configured to generate a first internal oscillator signal based on the input oscillator signal. The LO generator may include a frequency dividing circuit configured to generate a second internal oscillator signal based on dividing a frequency of the first internal oscillator signal. The LO generator may include an output buffer configured to generate the LO signal based on the second internal oscillator signal. The input buffer and the frequency dividing circuit may each be configured to receive a power voltage independently of the output buffer.

Abstract: A neural network optimizing device includes a performance estimating module that outputs estimated performance according to performing operations of a neural network based on limitation requirements on resources used to perform the operations of the neural network. A portion selecting module receives the estimated performance from the performance estimating module and selects a portion of the neural network which deviates from the limitation requirements. A new neural network generating module generates, through reinforcement learning, a subset by changing a layer structure included in the selected portion of the neural network, determines an optimal layer structure based on the estimated performance provided from the performance estimating module, and changes the selected portion to the optimal layer structure to generate a new neural network. A final neural network output module outputs the new neural network generated by the new neural network generating module as a final neural network.

Abstract: A semiconductor device is provided. The semiconductor device comprises a first memory unit including a first memory area, and a first logic area electrically connected to the first memory area, the first logic area including a cache memory and an interface port. The first memory unit executes a data transmission and reception operation with a memory unit adjacent to the first memory unit via the first interface port and the cache memory.

Abstract: A local oscillator generator (LO generator) may be configured to transmit an LO signal to a mixer. The LO generator may include an input buffer configured to generate a first internal oscillator signal based on the input oscillator signal. The LO generator may include a frequency dividing circuit configured to generate a second internal oscillator signal based on dividing a frequency of the first internal oscillator signal. The LO generator may include an output buffer configured to generate the LO signal based on the second internal oscillator signal. The input buffer and the frequency dividing circuit may each be configured to receive a power voltage independently of the output buffer.

Abstract: A local oscillator generator (LO generator) may be configured to transmit an LO signal to a mixer. The LO generator may include an input buffer configured to generate a first internal oscillator signal based on the input oscillator signal. The LO generator may include a frequency dividing circuit configured to generate a second internal oscillator signal based on dividing a frequency of the first internal oscillator signal. The LO generator may include an output buffer configured to generate the LO signal based on the second internal oscillator signal. The input buffer and the frequency dividing circuit may each be configured to receive a power voltage independently of the output buffer.

Abstract: A local oscillator generator (LO generator) may be configured to transmit an LO signal to a mixer. The LO generator may include an input buffer configured to generate a first internal oscillator signal based on the input oscillator signal. The LO generator may include a frequency dividing circuit configured to generate a second internal oscillator signal based on dividing a frequency of the first internal oscillator signal. The LO generator may include an output buffer configured to generate the LO signal based on the second internal oscillator signal. The input buffer and the frequency dividing circuit may each be configured to receive a power voltage independently of the output buffer.

Abstract: A quadrature signal phase controller includes a first phase shifter and a second phase shifter. The first phase shifter generates phase shifted first in-phase differential output signals and phase shifted first quadrature-phase differential output signals. The second phase shifter generates phase shifted second in-phase differential output signals and phase shifted second quadrature-phase differential output signals. Each of the first and second phase shifters increases or decreases the phase difference between the first in-phase differential output signals and the second quadrature-phase differential output signals, and the phase difference between the second in-phase differential output signals and the first quadrature-phase differential output signals, in response to a change in a level of the first control signal and a change in a level of the second control signal.

Abstract: A frequency divider includes a prescaler and multiple modulus dividers commonly coupled to the prescaler. The prescaler generates intermediate frequency signals having a same phase difference with respect to one another in response to an oscillation frequency signal. The prescaler operates at a first frequency. The modulus dividers respectively divide the intermediate frequency signals with respective ratio to provide a plurality of division frequency signals in response to a control signal. The modulus dividers operate at a second frequency less than the first frequency.

Abstract: A quadrature signal phase controller includes a first phase shifter and a second phase shifter. The first phase shifter generates phase shifted first in-phase differential output signals and phase shifted first quadrature-phase differential output signals. The second phase shifter generates phase shifted second in-phase differential output signals and phase shifted second quadrature-phase differential output signals. Each of the first and second phase shifters increases or decreases the phase difference between the first in-phase differential output signals and the second quadrature-phase differential output signals, and the phase difference between the second in-phase differential output signals and the first quadrature-phase differential output signals, in response to a change in a level of the first control signal and a change in a level of the second control signal.

Abstract: A quadrature signal phase controller includes a first phase shifter and a second phase shifter. The first phase shifter generates phase shifted first in-phase differential output signals and phase shifted first quadrature-phase differential output signals. The second phase shifter generates phase shifted second in-phase differential output signals and phase shifted second quadrature-phase differential output signals. Each of the first and second phase shifters increases or decreases the phase difference between the first in-phase differential output signals and the second quadrature-phase differential output signals, and the phase difference between the second in-phase differential output signals and the first quadrature-phase differential output signals, in response to a change in a level of the first control signal and a change in a level of the second control signal.

Abstract: A frequency synthesizer includes a distributed phase detector circuit, a multiple charge pump, a loop filter, a voltage-controlled oscillator and a dividing circuit. The distributed phase detector circuit delays an up signal and a down signal to generate a delayed up signal and a delayed down signal. The multiple charge pump generates a distributed current signal including a plurality of current pulse signals. Each of the current pulse signal is based on each bit of the delayed up signal and the delayed down signal. The loop filter filters the distributed current signal to generate a control voltage. The voltage-controlled oscillator generates an oscillation frequency signal based on the control voltage. The dividing circuit divides the oscillation frequency signal to generate a plurality of division frequency signals in response to a plurality of control signals, where the frequency signals are fedback to the distributed phase detector circuit.

Abstract: A frequency divider includes a prescaler and multiple modulus dividers commonly coupled to the prescaler. The prescaler generates intermediate frequency signals having a same phase difference with respect to one another in response to an oscillation frequency signal. The prescaler operates at a first frequency. The modulus dividers respectively divide the intermediate frequency signals with respective ratio to provide a plurality of division frequency signals in response to a control signal. The modulus dividers operate at a second frequency less than the first frequency.

Abstract: A quadrature signal phase controller includes a first phase shifter and a second phase shifter. The first phase shifter generates phase shifted first in-phase differential output signals and phase shifted first quadrature-phase differential output signals. The second phase shifter generates phase shifted second in-phase differential output signals and phase shifted second quadrature-phase differential output signals. Each of the first and second phase shifters increases or decreases the phase difference between the first in-phase differential output signals and the second quadrature-phase differential output signals, and the phase difference between the second in-phase differential output signals and the first quadrature-phase differential output signals, in response to a change in a level of the first control signal and a change in a level of the second control signal.

Abstract: A sigma-delta fractional-N phase locked loop has faster lock time with increased charge pump current and decreased loop filter resistance in the unlock state. On the other hand, the sigma-delta fractional-N phase locked loop has lower noise susceptibility and lower frequency error with gradual decrease in charge pump current and gradual increase in loop filter resistance, in the lock state.

Abstract: A sigma-delta fractional-N phase locked loop has faster lock time with increased charge pump current and decreased loop filter resistance in the unlock state. On the other hand, the sigma-delta fractional-N phase locked loop has lower noise susceptibility and lower frequency error with gradual decrease in charge pump current and gradual increase in loop filter resistance, in the lock state.

Abstract: A radar system using a quadrature signal includes a quadrature push—push oscillator for generating four harmonics with a 90-degree phase difference from each other, and producing two-balanced 2nd harmonic signals from the harmonics; a first coupler block for radiating one of the 2nd harmonics through an antenna; a second coupler block for terminating the other 2nd harmonic to ground; and a power combiner for combining a transmitted signal that is leaked from the first and second coupler blocks with the received signal that is radiated through the antenna. The radar system features an improved receiving sensitivity by offsetting the leakage signals of the sending end. Also, the radar system can be made very small by using a single antenna for transmitting and receiving.