Abstract: A semiconductor package includes a package substrate having opposing first and second surfaces, a control chip on the first surface, a mode selection connection terminal between the control chip and the package substrate, a stack structure comprising stacked memory chips spaced apart from the control chip on the first surface, a first power pad and a wire pad that are spaced apart at the first surface, a first external connection terminal on the second surface, and first and second interconnection lines in the package substrate. The first power pad and the wire pad are spaced apart from the control chip. The first interconnection line connects the first power pad to the first external connection terminal. The second interconnection line connects the wire pad to the mode selection connection terminal. The first external connection terminal is configured to provide a ground voltage or a power voltage.

Abstract: Disclosed is a semiconductor package comprising a substrate, a chip stack including semiconductor chips stacked in an ascending stepwise shape on the substrate, first power/ground wires through which the substrate is connected to a lowermost semiconductor chip of the chip stack and neighboring semiconductor chips of the chip stack are connected to each other, and a second power/ground wire that extends from a first semiconductor chip and is connected to the substrate. The first semiconductor chip is one semiconductor chip other than the lowermost semiconductor chip and an uppermost semiconductor chip of the chip stack. The chip stack includes a first stack and a second stack on the first stack. The second stack constitutes a channel separate from that of the first stack.

Abstract: A method of fabricating a semiconductor package includes preparing a panel package including a redistribution substrate, a connection substrate and a plurality of lower semiconductor chips; sawing the panel package to form a plurality of separated strip packages each of which includes the sawed redistribution substrate, at least two of the lower semiconductor chips, and the sawed connection substrate; and providing a plurality of upper semiconductor chips on one of the strip packages to electrically connect the upper semiconductor chips to the sawed connection substrate.

Abstract: A card-type solid state drive (SSD) including: a substrate that has a first surface and a second surface facing each other; a memory controller and a nonvolatile memory device that are on the first surface; a plurality of functional terminals on the second surface; and a plurality of thermal terminals on the second surface, wherein the functional terminals include first-row functional terminals, second-row functional terminals, and third-row functional terminals, wherein at least one of the first-row functional terminals, at least one of the second-row functional terminals, and at least one of the third-row functional terminals are electrically connected to the memory controller or the nonvolatile memory device, and wherein the thermal terminals are not electrically connected to the memory controller or the nonvolatile memory device.

Abstract: A method of fabricating a semiconductor package includes preparing a panel package including a redistribution substrate, a connection substrate and a plurality of lower semiconductor chips; sawing the panel package to form a plurality of separated strip packages each of which includes the sawed redistribution substrate, at least two of the lower semiconductor chips, and the sawed connection substrate; and providing a plurality of upper semiconductor chips on one of the strip packages to electrically connect the upper semiconductor chips to the sawed connection substrate.

Abstract: An electric apparatus includes a substrate having a ground pattern on a top surface of the substrate; a conductive housing on the ground pattern and having an insertion space; a conductive connector disposed between the ground pattern and the conductive housing and connected to the ground pattern and the conductive housing, wherein the conductive housing is fixed to the substrate via the conductive connector; and a conductive cover coupled to the conductive housing, wherein the conductive cover is configured to move from a first position, at which the conductive cover externally opens the insertion space, to a second position, at which the conductive cover closes the insertion space.

Abstract: Disclosed is a semiconductor package comprising a substrate, a chip stack including semiconductor chips stacked in an ascending stepwise shape on the substrate, first power/ground wires through which the substrate is connected to a lowermost semiconductor chip of the chip stack and neighboring semiconductor chips of the chip stack are connected to each other, and a second power/ground wire that extends from a first semiconductor chip and is connected to the substrate. The first semiconductor chip is one semiconductor chip other than the lowermost semiconductor chip and an uppermost semiconductor chip of the chip stack. The chip stack includes a first stack and a second stack on the first stack. The second stack constitutes a channel separate from that of the first stack.

Abstract: A method of fabricating a semiconductor package includes preparing a panel package including a redistribution substrate, a connection substrate and a plurality of lower semiconductor chips; sawing the panel package to form a plurality of separated strip packages each of which includes the sawed redistribution substrate, at least two of the lower semiconductor chips, and the sawed connection substrate; and providing a plurality of upper semiconductor chips on one of the strip packages to electrically connect the upper semiconductor chips to the sawed connection substrate.

Abstract: An electric apparatus includes a substrate having a ground pattern on a top surface of the substrate; a conductive housing on the ground pattern and having an insertion space; a conductive connector disposed between the ground pattern and the conductive housing and connected to the ground pattern and the conductive housing, wherein the conductive housing is fixed to the substrate via the conductive connector; and a conductive cover coupled to the conductive housing, wherein the conductive cover is configured to move from a first position, at which the conductive cover externally opens the insertion space, to a second position, at which the conductive cover closes the insertion space.

Abstract: A card-type solid state drive (SSD) including: a substrate that has a first surface and a second surface facing each other; a memory controller and a nonvolatile memory device that are on the first surface; a plurality of functional terminals on the second surface; and a plurality of thermal terminals on the second surface, wherein the functional terminals include first-row functional terminals, second-row functional terminals, and third-row functional terminals, wherein at least one of the first-row functional terminals, at least one of the second-row functional terminals, and at least one of the third-row functional terminals are electrically connected to the memory controller Or the nonvolatile memory device, and wherein the thermal terminals are not electrically connected to the memory controller or the nonvolatile memory device.

Abstract: A method of fabricating a semiconductor package includes preparing a panel package including a redistribution substrate, a connection substrate and a plurality of lower semiconductor chips; sawing the panel package to form a plurality of separated strip packages each of which includes the sawed redistribution substrate, at least two of the lower semiconductor chips, and the sawed connection substrate; and providing a plurality of upper semiconductor chips on one of the strip packages to electrically connect the upper semiconductor chips to the sawed connection substrate.

Abstract: A data storage device includes a controller connected via a plurality of channels to a plurality of clusters, wherein each cluster comprises a scale-out device including a scale-out controller and a buffer. The scale-out controller is connected to a plurality of sub-channels, each one of the plurality of sub-channels connecting a group of non-volatile memory (NVM) devices, such that the scale-out controller controls execution of data processing operations directed to any one of the NVM devices and the buffer.

Abstract: A solid-state drive (SSD) includes a main printed circuit board (PCB), and a first semiconductor package and a second semiconductor package respectively mounted on a top surface and a bottom surface of the main PCB. Each of the first and second semiconductor packages has a surface on which connection pads corresponding to a package ball map are disposed. The package ball map includes cells arranged in a plurality of rows and a plurality of columns, and one signal corresponds to each of the cells of the package ball map. The package ball map includes first signals corresponding to at least some of cells included in a selected reference column from among the plurality of columns, and at least one pair of second signals respectively corresponding to cells that are symmetrical to each other with respect to the reference column. The pair of second signals are swappable signals, and the first signals are not swappable signals.

Abstract: A solid state drive (SSD) package type has a lower package including a lower package substrate, a controller chip mounted on the lower package substrate, and a plurality of upper packages disposed on the lower package as spaced apart from each other. The plurality of upper packages includes at least one non-volatile memory and at least one first individual electronic component. The upper packages are electrically connected to the lower package such that the package type is a package-on-package (PoP) type. The height of the first individual electronic component is greater than the spacing between the lower package and each of the upper packages.

Abstract: A solid state drive (SSD) package type has a lower package including a lower package substrate, a controller chip mounted on the lower package substrate, and a plurality of upper packages disposed on the lower package as spaced apart from each other. The plurality of upper packages includes at least one non-volatile memory and at least one first individual electronic component. The upper packages are electrically connected to the lower package such that the package type is a package-on-package (PoP) type. The height of the first individual electronic component is greater than the spacing between the lower package and each of the upper packages.

Abstract: A solid-state drive (SSD) includes a main printed circuit board (PCB), and a first semiconductor package and a second semiconductor package respectively mounted on a top surface and a bottom surface of the main PCB. Each of the first and second semiconductor packages has a surface on which connection pads corresponding to a package ball map are disposed. The package ball map includes cells arranged in a plurality of rows and a plurality of columns, and one signal corresponds to each of the cells of the package ball map. The package ball map includes first signals corresponding to at least some of cells included in a selected reference column from among the plurality of columns, and at least one pair of second signals respectively corresponding to cells that are symmetrical to each other with respect to the reference column The pair of second signals are swappable signals, and the first signals are not swappable signals.

Abstract: A data storage device includes a controller connected via a plurality of channels to a plurality of clusters, wherein each cluster comprises a scale-out device including a scale-out controller and a buffer. The scale-out controller is connected to a plurality of sub-channels, each one of the plurality of sub-channels connecting a group of non-volatile memory (NVM) devices, such that the scale-out controller controls execution of data processing operations directed to any one of the NVM devices and the buffer.

Abstract: Provided is a semiconductor package including a plurality of first semiconductor chips that are stacked on a substrate and a second semiconductor chip disposed on the plurality of first semiconductor chips. The plurality of first semiconductor chips comprises a first semiconductor chip group and a second semiconductor chip group. The first semiconductor chip group is electrically connected to the second semiconductor chip through a first channel. The second semiconductor chip group is electrically connected to the second semiconductor chip through a second channel. At least one of the first channel and the second channel extends along a top surface of the first semiconductor chip which is disposed on the uppermost side, or top of the stack, among the plurality of first semiconductor chips. The inventive concept may provide the semiconductor package having a high operation speed, low power consumption, and a small thickness and capable of being manufactured at low costs.

Abstract: Provided is a semiconductor package including a plurality of first semiconductor chips that are stacked on a substrate and a second semiconductor chip disposed on the plurality of first semiconductor chips. The plurality of first semiconductor chips comprises a first semiconductor chip group and a second semiconductor chip group. The first semiconductor chip group is electrically connected to the second semiconductor chip through a first channel. The second semiconductor chip group is electrically connected to the second semiconductor chip through a second channel. At least one of the first channel and the second channel extends along a top surface of the first semiconductor chip which is disposed on the uppermost side, or top of the stack, among the plurality of first semiconductor chips. The inventive concept may provide the semiconductor package having a high operation speed, low power consumption, and a small thickness and capable of being manufactured at low costs.

Abstract: The present disclosure provides a memory device and a fabricating method thereof. The memory device includes a substrate including a first metal layer formed therein, the first metal layer having at least a first surface with at least a first exposed portion of the first surface exposed at a lateral surface of the substrate, at least a first semiconductor chip formed on a top surface of the substrate, and a second metal layer surrounding the first semiconductor chip and extending to lateral surfaces of the substrate, at least a first portion of the second metal layer contacting the exposed surface of the first metal layer.