Patents by Inventor Sang-Won Ha
Sang-Won Ha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250064379Abstract: A multi-bio-signal-based geriatric cognitive impairment diagnosis method includes collecting multiple bio-signals including brain waves, heart rate variability, and gait measurement values of a subject during walking; calculating a probability value of a geriatric cognitive impairment disease by using a cognitive impairment diagnosis model, based on the multiple bio-signals; and determining whether there is a geriatric cognitive impairment disease, based on a calculated probability value, wherein the cognitive impairment diagnosis model is a model constructed by applying brain waves, heart rate variability, and gait measurement values of a patient with a geriatric cognitive impairment disease to a logistic function.Type: ApplicationFiled: November 13, 2024Publication date: February 27, 2025Applicant: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Kyoung-Bok MIN, Jin-Young MIN, Sang-Won HA
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Patent number: 10572969Abstract: A method of processing data includes: generating at least one partial summed area table (SAT) by dividing data stored in a global memory, and obtaining a row sum and a column sum of each of the at least one partial SAT; performing propagation on the obtained row sums and column sums; when a process of utilizing the SAT is executed, completing at least a partial area of the SAT necessary for the process based on the at least one partial SAT, and the row sums and column sums on which the propagation has been performed; and performing the process by using the completed partial area.Type: GrantFiled: May 31, 2017Date of Patent: February 25, 2020Assignee: Samsung Electronics Co., Ltd.Inventor: Sang-won Ha
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Patent number: 10553024Abstract: A tile-based rendering method includes receiving a drawcall, determining a location of primitives in a frame based on the drawcall, dividing the frame into a plurality of tiles, and rendering the tiles, wherein the rendering includes determining a rendering order of the tiles based on primitives included in the tiles, and rendering the tiles according to the rendering order. A graphics processing unit (GPU) is configured to perform the tile-based rendering method, and may include a memory, a processor including at least one core and at least one cache. The GPU may execute a tile-based graphics pipeline for tile-based rendering of images, and allocate tiles including identical primitives to a core.Type: GrantFiled: May 25, 2017Date of Patent: February 4, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min-Kyu Jeong, Jae-Don Lee, Sang-Won Ha, Min-Young Son
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Patent number: 10331448Abstract: A method and a graphics processing apparatus for processing texture in a graphics pipeline determine a rendering level of a dynamic texture based on usage information of a target object and render the target object by texturing the target object with the dynamic texture rendered based on the rendering level. The graphics processing apparatus includes at least one cache memory, and at least one processor configured to: perform geometry processing of a dynamic texture to be mapped onto a target object, determine a rendering level of the dynamic texture based on usage information of the target object obtained by the geometry processing of the target object, render the dynamic texture based on the determined rendering level, and render the target object by texturing the target object with the rendered dynamic texture.Type: GrantFiled: June 20, 2017Date of Patent: June 25, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min-Young Son, Kwon-Taek Kwon, Jae-Don Lee, Min-Kyu Jeong, Sang-Won Ha
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Publication number: 20180150296Abstract: A method and a graphics processing apparatus for processing texture in a graphics pipeline determine a rendering level of a dynamic texture based on usage information of a target object and render the target object by texturing the target object with the dynamic texture rendered based on the rendering level. The graphics processing apparatus includes at least one cache memory, and at least one processor configured to: perform geometry processing of a dynamic texture to be mapped onto a target object, determine a rendering level of the dynamic texture based on usage information of the target object obtained by the geometry processing of the target object, render the dynamic texture based on the determined rendering level, and render the target object by texturing the target object with the rendered dynamic texture.Type: ApplicationFiled: June 20, 2017Publication date: May 31, 2018Inventors: MIN-YOUNG SON, KWON-TAEK KWON, JAE-DON LEE, MIN-KYU JEONG, SANG-WON HA
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Publication number: 20180137600Abstract: A method of processing data includes: generating at least one partial summed area table (SAT) by dividing data stored in a global memory, and obtaining a row sum and a column sum of each of the at least one partial SAT; performing propagation on the obtained row sums and column sums; when a process of utilizing the SAT is executed, completing at least a partial area of the SAT necessary for the process based on the at least one partial SAT, and the row sums and column sums on which the propagation has been performed; and performing the process by using the completed partial area.Type: ApplicationFiled: May 31, 2017Publication date: May 17, 2018Applicant: Samsung Electronics Co., Ltd.Inventor: Sang-won HA
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Publication number: 20180137677Abstract: A tile-based rendering method includes receiving a drawcall, determining a location of primitives in a frame based on the drawcall, dividing the frame into a plurality of tiles, and rendering the tiles, wherein the rendering includes determining a rendering order of the tiles based on primitives included in the tiles, and rendering the tiles according to the rendering order. A graphics processing unit (GPU) is configured to perform the tile-based rendering method, and may include a memory, a processor including at least one core and at least one cache. The GPU may execute a tile-based graphics pipeline for tile-based rendering of images, and allocate tiles including identical primitives to a core.Type: ApplicationFiled: May 25, 2017Publication date: May 17, 2018Inventors: MIN-KYU JEONG, JAE-DON LEE, SANG-WON HA, MIN-YOUNG SON
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Publication number: 20160338211Abstract: A circuit board includes a top surface; a bottom surface; and a heat-dissipating portion, wherein the heat-dissipating portion extends from the top surface of the circuit board to the bottom surface of the circuit board, and a first surface of the heat-dissipating portion is exposed out of the top surface of the circuit board, and a second surface of the heat-dissipating portion is exposed out of the bottom surface of the circuit board.Type: ApplicationFiled: March 28, 2016Publication date: November 17, 2016Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Sang-Won HA, Tae-Gon LEE, Kwang-Hee KWON
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Publication number: 20080022072Abstract: A system, method and medium performing data operations according to a merged multi-threading and out-of-order scheme. According to the method, at least one instruction is decoded, a thread of an instruction is read based on the decoding result, and a predetermined operation is performed on each of a plurality of threads, including the read thread, in each of a plurality of pipeline stages in an out-of-order manner, based on the decoding result. Accordingly, it is possible to guarantee high throughput while maintaining a small number of threads.Type: ApplicationFiled: June 5, 2007Publication date: January 24, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok-yoon Jung, Sang-won Ha, Do-kyoon Kim, Won-jong Lee, Seung-gi Lee
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Patent number: 7280716Abstract: Disclosed is a PCB in which a waveguide is embedded, and a method of producing the same. The PCB includes a substrate, and a lower clad layer formed on the substrate through a predetermined process to allow an optical signal irradiated thereto to be total-reflected thereby. A core layer is formed on the lower clad layer through a predetermined process and exposed using an exposing film on which a waveguide pattern is formed to form the waveguide with a predetermined shape therefrom. Furthermore, an upper clad layer is formed on the core layer through a predetermined process to allow the optical signal irradiated thereto to be total-reflected thereby.Type: GrantFiled: March 1, 2007Date of Patent: October 9, 2007Assignee: Samsung Electro-Mechanics Co., LtdInventors: Sang-Won Ha, Byoung-Ho Rhee, Keun-Ho Kim, Kyoung-Up Shin, Dek-Gin Yang
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Publication number: 20070154134Abstract: Disclosed is a PCB in which a waveguide is embedded, and a method of producing the same. The PCB includes a substrate, and a lower clad layer formed on the substrate through a predetermined process to allow an optical signal irradiated thereto to be total-reflected thereby. A core layer is formed on the lower clad layer through a predetermined process and exposed using an exposing film on which a waveguide pattern is formed to form the waveguide with a predetermined shape therefrom. Furthermore, an upper clad layer is formed on the core layer through a predetermined process to allow the optical signal irradiated thereto to be total-reflected thereby.Type: ApplicationFiled: March 1, 2007Publication date: July 5, 2007Inventors: Sang-Won Ha, Byoung-Ho Rhee, Keun-Ho Kim, Kyoung-UP Shin, Dek-Gin Yang
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Patent number: 7203388Abstract: Disclosed is a PCB in which a waveguide is embedded, and a method of producing the same. The PCB includes a substrate, and a lower clad layer formed on the substrate through a predetermined process to allow an optical signal irradiated thereto to be total-reflected thereby. A core layer is formed on the lower clad layer through a predetermined process and exposed using an exposing film on which a waveguide pattern is formed to form the waveguide with a predetermined shape therefrom. Furthermore, an upper clad layer is formed on the core layer through a predetermined process to allow the optical signal irradiated thereto to be total-reflected thereby.Type: GrantFiled: May 14, 2004Date of Patent: April 10, 2007Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Sang-Won Ha, Byoung-Ho Rhee, Keun-Ho Kim, Kyoung-Up Shin, Dek-Gin Yang
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Publication number: 20050106368Abstract: Disclosed is a PCB in which copper clads are formed on both sides or any one side of a semicured prepreg having a structure that optical fibers disposed at regular intervals by fixing jigs are embedded in an epoxy resin, and a method of producing the same. Furthermore, the present invention provides a PCB, in which copper clads are formed on both sides or any one side of a semicured prepreg having a structure that a waveguide layer to transmit an optical signal therethrough is embedded in an epoxy resin.Type: ApplicationFiled: March 2, 2004Publication date: May 19, 2005Inventors: Sang-Won Ha, Byoung-Ho Rhee, Kyoung-Hwan Lim, Kyoung-Up Shin, Dek-Gin Yang
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Publication number: 20050094922Abstract: Disclosed is a PCB in which a waveguide is embedded, and a method of producing the same. The PCB includes a substrate, and a lower clad layer formed on the substrate through a predetermined process to allow an optical signal irradiated thereto to be total-reflected thereby. A core layer is formed on the lower clad layer through a predetermined process and exposed using an exposing film on which a waveguide pattern is formed to form the waveguide with a predetermined shape therefrom. Furthermore, an upper clad layer is formed on the core layer through a predetermined process to allow the optical signal irradiated thereto to be total-reflected thereby.Type: ApplicationFiled: May 14, 2004Publication date: May 5, 2005Inventors: Sang-Won Ha, Byoung-Ho Rhee, Keun-Ho Kim, Kyoung-Up Shin, Dek-Gin Yang