Abstract: In a method of operating a storage device including at least one nonvolatile memory device and a memory controller configured to control the at least one nonvolatile memory device, a boundary page of a first memory block among a plurality of memory blocks included in the at least one nonvolatile memory device is searched for, at least one clean page, in which data is not written, of the first memory block is searched for, a dummy program operation is performed on a portion of the boundary page and the at least one clean page, and an erase operation is performed on the first memory block.

Abstract: In a method of operating a storage device including at least one nonvolatile memory device and a memory controller configured to control the at least one nonvolatile memory device, a boundary page of a first memory block among a plurality of memory blocks included in the at least one nonvolatile memory device is searched for, at least one clean page, in which data is not written, of the first memory block is searched for, a dummy program operation is performed on a portion of the boundary page and the at least one clean page, and an erase operation is performed on the first memory block.

Abstract: To program in a nonvolatile memory device include a plurality of memory cells that are programmed into multiple states through at least two program steps, a primary program is performed from an erase level to a first target level with respect to the memory cells coupled to a selected word line A preprogram is performed from the erase level to a preprogram level in association with the primary program with respect to the memory cells coupled to the selected word line, where the preprogram level is larger than the erase level and smaller than the first target level A secondary program is performed from the preprogram level to a second target level with respect to the preprogrammed memory cells coupled to the selected word line.

Abstract: To program in a nonvolatile memory device include a plurality of memory cells that are programmed into multiple states through at least two program steps, a primary program is performed from an erase level to a first target level with respect to the memory cells coupled to a selected word line A preprogram is performed from the erase level to a preprogram level in association with the primary program with respect to the memory cells coupled to the selected word line, where the preprogram level is larger than the erase level and smaller than the first target level A secondary program is performed from the preprogram level to a second target level with respect to the preprogrammed memory cells coupled to the selected word line.

Abstract: A method of programming memory cells for a non-volatile memory device is provided. The method includes performing an incremental step pulse program (ISPP) operation based on a program voltage, a first verification voltage, and a second verification voltage, and changing an increment value of the program voltage based on a first pass-fail result of the memory cells, the first pass-fail result being generated based on the first verification voltage. The ISPP operation is finished based on a second pass-fail result of the memory cells, the second pass-fail result being generated based on the second verification voltage.

Abstract: In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well.

Abstract: In a method of reading data from a non-volatile memory device, read data is generated based on a word line voltage. The read data includes data read from a plurality of sectors included in the non-volatile memory device. Bad sector data is transferred data based on read data and bad sector information. The bad sector data corresponds to data read from at least one bad sector included in the plurality of sectors. The bad sector information is updated by checking error bits of the bad sector data. The word line voltage is generated based on the updated bad sector information.

Abstract: A nonvolatile memory device includes a plurality of memory cells connected to a wordline and arranged in a row direction, bitlines connected to the plurality of memory cells, respectively, and a bitline bias circuit configured to separately control bias voltages provided to the bitlines according to positions of the memory cells along the row direction.

Abstract: In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well.

Abstract: In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line; and the de-coupling transistor is formed in the well.

Abstract: A method of programming memory cells for a non-volatile memory device is provided. The method includes performing an incremental step pulse program (ISPP) operation based on a program voltage, a first verification voltage, and a second verification voltage, and changing an increment value of the program voltage based on a first pass-fail result of the memory cells, the first pass-fail result being generated based on the first verification voltage. The ISPP operation is finished based on a second pass-fail result of the memory cells, the second pass-fail result being generated based on the second verification voltage.

Abstract: A flash memory device including a high voltage generator circuit that is adapted to supply a program voltage having a target voltage to a selected word line is provided. The flash memory device is adapted to terminate the program interval in accordance with when the program voltage has been restored to the target voltage after dropping below the target voltage. A method for operating the flash memory device is also provided.

Abstract: A non-volatile memory may include a flag cell array, wherein each flag cell is arranged in the memory cell array interspersed among the plurality of memory cells. The flag cell array may include a plurality of flag cells indicating whether a corresponding row is MSB programmed. The non-volatile memory device performs an algorithm to read out data stored in the memory cell based on whether the memory cells of a row are MSB programmed. When determining whether the corresponding row is MSB programmed, a flag cell that is not normally operated may be replaced by a redundancy flag cell or data of the flag cell that is not normally operated may be excluded. Thus, the reliability in reading out of data and the production yield of the non-volatile memory may be improved.

Abstract: In a read method for a memory device, a bit line is set with data in a first memory cell; and the data on the bit line is stored in a register. The data in the register is transferred to a data bus while setting the bit line with data in a second memory cell. In another read method for a memory device, a bit line of a first memory cell is initialized and the bit line is pre-charged with a pre-charge voltage. Data in a memory cell on the bit line is developed, and a register corresponding to the bit line is initialized. The data on the bit line is stored in the register. The data in the register is output externally while performing the initializing, pre-charging, making and initializing to set the bit line with data in a second memory cell.

Abstract: A flash memory device is disclosed and includes a memory cell array including a plurality of sectors. Each one of the plurality of sectors includes a plurality of strings, and each of the plurality of strings includes a plurality of memory cells series connected between a string select transistor and a ground select transistor. The flash memory device also includes a plurality of string selection lines, wherein each one of the plurality of string selection lines is respectively connected to string select transistors associated the plurality of strings in one of the plurality of sectors.

Abstract: In a flash memory device, different self-boosting techniques are selectively applied to a string of serially connected memory cells responsive to a programming voltage applied to a selected word line. For example, non-local self-boosting and local self-boosting may be selectively applied responsive to the programming voltage applied to the selected word line. For example, non-local self-boosting and local self-boosting may be selectively applied to a first string of serially-connected cells responsive to the programming voltage during an incremental step pulse programming (ISPP) of a selected cell of a second string of serially-connected cells.

Abstract: In a method of reading data from a non-volatile memory device, read data is generated based on a word line voltage. The read data includes data read from a plurality of sectors included in the non-volatile memory device. Bad sector data is transferred data based on read data and bad sector information. The bad sector data corresponds to data read from at least one bad sector included in the plurality of sectors. The bad sector information is updated by checking error bits of the bad sector data. The word line voltage is generated based on the updated bad sector information.

Abstract: In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line; and the de-coupling transistor is formed in the well.

Abstract: A nonvolatile memory device, memory system and read method are disclosed. The memory device comprises a memory cell array comprising a plurality of memory blocks each having a plurality of memory cells adapted to store N bits, where N is an integer greater than 1, a page buffer configured to perform a read operation adapted to read data from the memory cell array and output read data, an error correction circuit configured to detect and correct an error in read data stored in a memory block K and generate corresponding error information, and a control circuit configured to reduce the number of bits stored in the plurality of memory cells for memory block K from N to J, where J is an integer less than N but greater than zero, in response to the error information.

Abstract: In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well.