Abstract: A method of implementing engine braking using a virtual gear shift (VGS) system of an electric vehicle (EV), which is connected with a VGS mode torque profile map, performs power-off down shift control by turning a VGS function on in response to an accelerator position scope (APS) off signal and a paddle shift signal. The method performs shift progress using a gear shift feeling torque compensating for a torque difference between a target gear shift stage and a current gear shift stage of the VGS. The method also controls vehicle deceleration to allow an amount of regenerative braking to increase using a target coasting torque as a gear is shifted to a lower gear shift stage to implement an engine braking feeling due to an increase in a deceleration feeling after the gear is shift.

Abstract: A method of implementing engine braking using a virtual gear shift (VGS) system of an electric vehicle (EV), which is connected with a VGS mode torque profile map, performs power-off down shift control by turning a VGS function on in response to an accelerator position scope (APS) off signal and a paddle shift signal. The method performs shift progress using a gear shift feeling torque compensating for a torque difference between a target gear shift stage and a current gear shift stage of the VGS. The method also controls vehicle deceleration to allow an amount of regenerative braking to increase using a target coasting torque as a gear is shifted to a lower gear shift stage to implement an engine braking feeling due to an increase in a deceleration feeling after the gear is shift.

Abstract: A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation regions; gate patterns formed in a step structure over a border region between individual first active regions and second active region, wherein one side of the individual gate pattern is formed over a portion of the individual first active region, and the other side of the individual gate pattern is formed over a portion of the second active region; spacers formed on lateral walls of the gate patterns; first cell junction regions formed in the first active regions, for connecting to storage nodes; and a second cell junction region formed in the second active region, for connecting to a bit line.

Abstract: A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation regions; gate patterns formed in a step structure over a border region between individual first active regions and second active region, wherein one side of the individual gate pattern is formed over a portion of the individual first active region, and the other side of the individual gate pattern is formed over a portion of the second active region; spacers formed on lateral walls of the gate patterns; first cell junction regions formed in the first active regions, for connecting to storage nodes; and a second cell junction region formed in the second active region, for connecting to a bit line.

Abstract: A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation regions; gate patterns formed in a step structure over a border region between individual first active regions and second active region, wherein one side of the individual gate pattern is formed over a portion of the individual first active region, and the other side of the individual gate pattern is formed over a portion of the second active region; spacers formed on lateral walls of the gate patterns; first cell junction regions formed in the first active regions, for connecting to storage nodes; and a second cell junction region formed in the second active region, for connecting to a bit line.

Abstract: Storing parity information in an external storage with multiple disk drives by determining the number of the storage blocks used as data blocks and the number of the storage blocks used as parity blocks; forming a three-dimensional block matrix of virtual data blocks corresponding to the determined number of the storage blocks; allocating virtual parity blocks to the virtual data block planes; allocating the virtual data blocks and the virtual parity blocks to the storage blocks; calculating parity information based upon data bits respectively stored in the storage blocks corresponding to the virtual data blocks of every virtual data block plane; and storing the calculated parity information in the storage blocks corresponding to the virtual parity blocks. The stored parity information allows any number of error blocks to be recovered, and more particularly allow three or more error blocks per one parity group to be recovered.

Abstract: The semiconductor device includes a substrate including a first active region and a second active region having a greater height than that of the first active region. A gate pattern has a step structure, which is formed on a border region between the first active region and the second active region. The gate pattern extends from a predetermined portion of the first active region to a predecided portion of the second active region. Gate spacers are formed on both sidewalls of the gate pattern. A first cell junction is formed in the first active region at one gate spacer and connected to a storage node contact. A second cell junction is formed in the second active region at the other gate spacer and connected to a bit line contact.

Abstract: The semiconductor device includes a substrate including a first active region and a second active region having a greater height than that of the first active region. A gate pattern has a step structure, which is formed on a border region between the first active region and the second active region. The gate pattern extends from a predetermined portion of the first active region to a predecided portion of the second active region. Gate spacers are formed on both sidewalls of the gate pattern. A first cell junction is formed in the first active region at one gate spacer and connected to a storage node contact. A second cell junction is formed in the second active region at the other gate spacer and connected to a bit line contact.

Abstract: A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation regions; gate patterns formed in a step structure over a border region between individual first active regions and second active region, wherein one side of the individual gate pattern is formed over a portion of the individual first active region, and the other side of the individual gate pattern is formed over a portion of the second active region; spacers formed on lateral walls of the gate patterns; first cell junction regions formed in the first active regions, for connecting to storage nodes; and a second cell junction region formed in the second active region, for connecting to a bit line.

Abstract: Storing parity information in an external storage with multiple disk drives by determining the number of the storage blocks used as data blocks and the number of the storage blocks used as parity blocks; forming a three-dimensional block matrix of virtual data blocks corresponding to the determined number of the storage blocks; allocating virtual parity blocks to the virtual data block planes; allocating the virtual data blocks and the virtual parity blocks to the storage blocks; calculating parity information based upon data bits respectively stored in the storage blocks corresponding to the virtual data blocks of every virtual data block plane; and storing the calculated parity information in the storage blocks corresponding to the virtual parity blocks. The stored parity information allows any number of error blocks to be recovered, and more particularly allow three or more error blocks per one parity group to be recovered.