Abstract: This application relates to an optical sensor element. In one aspect, the optical sensor element includes a graphite column including one or more graphite rods. The optical sensor element may also include one or more first graphene layers partly or entirely covering each of both ends of the graphite column. The optical sensor element may further include one or more second graphene layers partly or entirely covering the outer circumferential surface of the graphite column. This application also relates to an optical sensor for measuring the concentration of a greenhouse gas and the optical sensor includes the optical sensor element.

Abstract: Provided are a process for preparing (3R,4R)-1-benzyl-N,4-dimethylpiperidin-3-amine or a salt thereof, which is an intermediate useful for the preparation of tofacitinib, an intermediate used in the process, i.e., isopropanol solvate of methyl ((3R,4R)-1-benzyl-4-methylpiperidin-3-yl)carbamate dibenzoyl-L-tartrate, an intermediate, having excellent stability, useful for the preparation of tofacitinib, i.e., (3R,4R)-1-benzyl-N,4-dimethylpiperidin-3-amine acetate, and a process for preparing tofacitinib or a pharmaceutically acceptable salt thereof.

Abstract: An aspect of the present invention provides a rechargeable battery which makes placement of the electrode assembly in the case during assembly easy. The rechargeable battery includes an electrode assembly including a first electrode, a separator, and a second electrode, a case housing the electrode assembly and having an opening in a plane parallel to a flat side surface of the electrode assembly, the case being electrically connected to the first electrode, a cover closing the opening in the case, and an electrode terminal mounted to a terminal opening in the case and connected to the second electrode, wherein the electrode terminal and the second electrode are insulated from the case.

Abstract: Disclosed is a method and apparatus for measuring magnetic field and/or temperature using a diamond nitrogen-vacancy center sensor, and a measuring apparatus based on a diamond nitrogen-vacancy center (DNV) sensor may include: a diamond nitrogen-vacancy center sensor; a frequency synthesizer for generating a first reference signal and a second reference signal; a first microwave generator for generating a first microwave that is frequency modulated according to the first reference signal and causes a first spin transition in the diamond nitrogen-vacancy center sensor; a second microwave generator for generating a second microwave that is frequency modulated according to the second reference signal and causes a second spin transition in the diamond nitrogen-vacancy center sensor; a laser irradiator for applying a laser to excite the spin state of the diamond nitrogen-vacancy center sensor; a power amplifier for combining and amplifying the first microwave and the second microwave to apply to the diamond nitrog

Abstract: A method of implementing engine braking using a virtual gear shift (VGS) system of an electric vehicle (EV), which is connected with a VGS mode torque profile map, performs power-off down shift control by turning a VGS function on in response to an accelerator position scope (APS) off signal and a paddle shift signal. The method performs shift progress using a gear shift feeling torque compensating for a torque difference between a target gear shift stage and a current gear shift stage of the VGS. The method also controls vehicle deceleration to allow an amount of regenerative braking to increase using a target coasting torque as a gear is shifted to a lower gear shift stage to implement an engine braking feeling due to an increase in a deceleration feeling after the gear is shift.

Abstract: Disclosed is a method and apparatus for measuring magnetic field and/or temperature using a diamond nitrogen-vacancy center sensor, and a measuring apparatus based on a diamond nitrogen-vacancy center (DNV) sensor may include: a diamond nitrogen-vacancy center sensor; a frequency synthesizer for generating a first reference signal and a second reference signal; a first microwave generator for generating a first microwave that is frequency modulated according to the first reference signal and causes a first spin transition in the diamond nitrogen-vacancy center sensor; a second microwave generator for generating a second microwave that is frequency modulated according to the second reference signal and causes a second spin transition in the diamond nitrogen-vacancy center sensor; a laser irradiator for applying a laser to excite the spin state of the diamond nitrogen-vacancy center sensor; a power amplifier for combining and amplifying the first microwave and the second microwave to apply to the diamond nitrog

Abstract: A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation regions; gate patterns formed in a step structure over a border region between individual first active regions and second active region, wherein one side of the individual gate pattern is formed over a portion of the individual first active region, and the other side of the individual gate pattern is formed over a portion of the second active region; spacers formed on lateral walls of the gate patterns; first cell junction regions formed in the first active regions, for connecting to storage nodes; and a second cell junction region formed in the second active region, for connecting to a bit line.

Abstract: A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation regions; gate patterns formed in a step structure over a border region between individual first active regions and second active region, wherein one side of the individual gate pattern is formed over a portion of the individual first active region, and the other side of the individual gate pattern is formed over a portion of the second active region; spacers formed on lateral walls of the gate patterns; first cell junction regions formed in the first active regions, for connecting to storage nodes; and a second cell junction region formed in the second active region, for connecting to a bit line.

Abstract: A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation regions; gate patterns formed in a step structure over a border region between individual first active regions and second active region, wherein one side of the individual gate pattern is formed over a portion of the individual first active region, and the other side of the individual gate pattern is formed over a portion of the second active region; spacers formed on lateral walls of the gate patterns; first cell junction regions formed in the first active regions, for connecting to storage nodes; and a second cell junction region formed in the second active region, for connecting to a bit line.

Abstract: Storing parity information in an external storage with multiple disk drives by determining the number of the storage blocks used as data blocks and the number of the storage blocks used as parity blocks; forming a three-dimensional block matrix of virtual data blocks corresponding to the determined number of the storage blocks; allocating virtual parity blocks to the virtual data block planes; allocating the virtual data blocks and the virtual parity blocks to the storage blocks; calculating parity information based upon data bits respectively stored in the storage blocks corresponding to the virtual data blocks of every virtual data block plane; and storing the calculated parity information in the storage blocks corresponding to the virtual parity blocks. The stored parity information allows any number of error blocks to be recovered, and more particularly allow three or more error blocks per one parity group to be recovered.

Abstract: The semiconductor device includes a substrate including a first active region and a second active region having a greater height than that of the first active region. A gate pattern has a step structure, which is formed on a border region between the first active region and the second active region. The gate pattern extends from a predetermined portion of the first active region to a predecided portion of the second active region. Gate spacers are formed on both sidewalls of the gate pattern. A first cell junction is formed in the first active region at one gate spacer and connected to a storage node contact. A second cell junction is formed in the second active region at the other gate spacer and connected to a bit line contact.

Abstract: A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation regions; gate patterns formed in a step structure over a border region between individual first active regions and second active region, wherein one side of the individual gate pattern is formed over a portion of the individual first active region, and the other side of the individual gate pattern is formed over a portion of the second active region; spacers formed on lateral walls of the gate patterns; first cell junction regions formed in the first active regions, for connecting to storage nodes; and a second cell junction region formed in the second active region, for connecting to a bit line.

Abstract: The semiconductor device includes a substrate including a first active region and a second active region having a greater height than that of the first active region. A gate pattern has a step structure, which is formed on a border region between the first active region and the second active region. The gate pattern extends from a predetermined portion of the first active region to a predecided portion of the second active region. Gate spacers are formed on both sidewalls of the gate pattern. A first cell junction is formed in the first active region at one gate spacer and connected to a storage node contact. A second cell junction is formed in the second active region at the other gate spacer and connected to a bit line contact.

Abstract: Storing parity information in an external storage with multiple disk drives by determining the number of the storage blocks used as data blocks and the number of the storage blocks used as parity blocks; forming a three-dimensional block matrix of virtual data blocks corresponding to the determined number of the storage blocks; allocating virtual parity blocks to the virtual data block planes; allocating the virtual data blocks and the virtual parity blocks to the storage blocks; calculating parity information based upon data bits respectively stored in the storage blocks corresponding to the virtual data blocks of every virtual data block plane; and storing the calculated parity information in the storage blocks corresponding to the virtual parity blocks. The stored parity information allows any number of error blocks to be recovered, and more particularly allow three or more error blocks per one parity group to be recovered.