Abstract: A drug administration management system according to an embodiment of the present disclosure may include a smart case configured to accommodate a drug administration device, display drug administration information including whether or not a drug is administered and a drug administration dose for each drug administration site input button based on an input of a user, and transmit the drug administration information externally; and a terminal configured to receive the externally transmitted drug administration information from the smart case, and monitor the drug administration information based on a drug administration plan input from a user.

Abstract: An apparatus for manufacturing a pouch-type rechargeable battery includes a preforming portion forming a folding groove in a portion of a protrusion of the pouch-type rechargeable battery, a folding portion disposed on a rear end of the preforming portion and folding the protrusion along the folding groove, a rolling portion disposed on a rear end of the folding portion and pressing the folded protrusion, and a pressing portion disposed on a rear end of the rolling portion and fixing the folded protrusion.

Abstract: The present invention provides a pharmaceutical composition for prevention or treatment of a stress disease and depression, the pharmaceutical composition be safely useable without toxicity and side effects by using an extract of leaves of Vaccinium bracteatum Thunb., which is natural resource of Korea, so that the reduction of manufacturing and production costs and the import substitution and export effects can be expected through the replacement of a raw material for preparation with a plant inhabiting in nature.

Abstract: Disclosed are a separator for fuel cells capable of minimizing the volume of a system and the use of sealants, and a stack for fuel cells, more particularly, a stack for solid oxide fuel cells, including the same. Specifically, by adding a metal sheet having a specific shape, position and size to the separator, the stress applied to the sealant can be uniformized, and thus the oxidizing agent and fuel can be separated and electrically isolated using only a piece of sealant. Therefore, the stack for fuel cells is characterized in that there is no variation in temperature, reactant concentration, power, or the like between respective unit cells, so delamination and microcracks do not occur, the volume is minimized, and the power density per unit volume is very high.

Abstract: A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation regions; gate patterns formed in a step structure over a border region between individual first active regions and second active region, wherein one side of the individual gate pattern is formed over a portion of the individual first active region, and the other side of the individual gate pattern is formed over a portion of the second active region; spacers formed on lateral walls of the gate patterns; first cell junction regions formed in the first active regions, for connecting to storage nodes; and a second cell junction region formed in the second active region, for connecting to a bit line.

Abstract: A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation regions; gate patterns formed in a step structure over a border region between individual first active regions and second active region, wherein one side of the individual gate pattern is formed over a portion of the individual first active region, and the other side of the individual gate pattern is formed over a portion of the second active region; spacers formed on lateral walls of the gate patterns; first cell junction regions formed in the first active regions, for connecting to storage nodes; and a second cell junction region formed in the second active region, for connecting to a bit line.

Abstract: A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation regions; gate patterns formed in a step structure over a border region between individual first active regions and second active region, wherein one side of the individual gate pattern is formed over a portion of the individual first active region, and the other side of the individual gate pattern is formed over a portion of the second active region; spacers formed on lateral walls of the gate patterns; first cell junction regions formed in the first active regions, for connecting to storage nodes; and a second cell junction region formed in the second active region, for connecting to a bit line.

Abstract: Storing parity information in an external storage with multiple disk drives by determining the number of the storage blocks used as data blocks and the number of the storage blocks used as parity blocks; forming a three-dimensional block matrix of virtual data blocks corresponding to the determined number of the storage blocks; allocating virtual parity blocks to the virtual data block planes; allocating the virtual data blocks and the virtual parity blocks to the storage blocks; calculating parity information based upon data bits respectively stored in the storage blocks corresponding to the virtual data blocks of every virtual data block plane; and storing the calculated parity information in the storage blocks corresponding to the virtual parity blocks. The stored parity information allows any number of error blocks to be recovered, and more particularly allow three or more error blocks per one parity group to be recovered.

Abstract: The semiconductor device includes a substrate including a first active region and a second active region having a greater height than that of the first active region. A gate pattern has a step structure, which is formed on a border region between the first active region and the second active region. The gate pattern extends from a predetermined portion of the first active region to a predecided portion of the second active region. Gate spacers are formed on both sidewalls of the gate pattern. A first cell junction is formed in the first active region at one gate spacer and connected to a storage node contact. A second cell junction is formed in the second active region at the other gate spacer and connected to a bit line contact.

Abstract: The semiconductor device includes a substrate including a first active region and a second active region having a greater height than that of the first active region. A gate pattern has a step structure, which is formed on a border region between the first active region and the second active region. The gate pattern extends from a predetermined portion of the first active region to a predecided portion of the second active region. Gate spacers are formed on both sidewalls of the gate pattern. A first cell junction is formed in the first active region at one gate spacer and connected to a storage node contact. A second cell junction is formed in the second active region at the other gate spacer and connected to a bit line contact.

Abstract: A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation regions; gate patterns formed in a step structure over a border region between individual first active regions and second active region, wherein one side of the individual gate pattern is formed over a portion of the individual first active region, and the other side of the individual gate pattern is formed over a portion of the second active region; spacers formed on lateral walls of the gate patterns; first cell junction regions formed in the first active regions, for connecting to storage nodes; and a second cell junction region formed in the second active region, for connecting to a bit line.

Abstract: Storing parity information in an external storage with multiple disk drives by determining the number of the storage blocks used as data blocks and the number of the storage blocks used as parity blocks; forming a three-dimensional block matrix of virtual data blocks corresponding to the determined number of the storage blocks; allocating virtual parity blocks to the virtual data block planes; allocating the virtual data blocks and the virtual parity blocks to the storage blocks; calculating parity information based upon data bits respectively stored in the storage blocks corresponding to the virtual data blocks of every virtual data block plane; and storing the calculated parity information in the storage blocks corresponding to the virtual parity blocks. The stored parity information allows any number of error blocks to be recovered, and more particularly allow three or more error blocks per one parity group to be recovered.