Abstract: A display apparatus includes a display panel for displaying an image, and a window substrate covering the display panel, the window substrate including a base substrate having a display area and a non-display area, a first printing layer at the base substrate, corresponding to the non-display area, and defining a logo hole, a logo pattern at the first printing layer and corresponding to the non-display area, a portion of the logo pattern being exposed through the logo hole, and a second printing layer at the logo pattern and spaced from the first printing layer with the logo pattern therebetween.

Abstract: In one embodiment, a method includes detecting user input linked to a portion of a graphical user interface associated with one or more applications. The method further includes rendering, in response to the detected user input, at least a portion of a transient graphical object that is made up of several portions. Each portion is associated with a different virtual space, and each portion contains content including at least: 1) information linked to a particular one of the one or more applications; and 2) one or more graphical control objects for initiating one or more actions linked to the particular application.

Abstract: In one embodiment, a method includes presenting to a user, on a display of a head-worn client computing device, a three-dimensional video including images of a real-life scene that is remote from the user's physical environment. The method also includes presenting to the user, on the display of the head-worn client computing device, a graphical object including an image of the user's physical environment or a virtual graphical object.

Abstract: Disclosed herein are a delay-locked loop circuit using a phase inversion locking algorithm and a method of controlling the same. There is provided a delay-locked loop circuit using a phase inversion locking algorithm, including a phase inversion controller configured to control whether or not to use the phase inversion locking algorithm by determining a phase error between an input clock signal and an output clock signal, an inverter configured to invert the input clock signal and output the inverted input clock signal, a multiplexer configured to receive the input clock signal and the inverted input clock signal of the inverter and output the input clock signal in response to the control signal of the phase inversion controller or the inverted input clock signal, and a delay-locked loop connected to the output terminal of the multiplexer and configured to perform phase synchronization in response to the output signal of the multiplexer.

Abstract: A transistor bias circuit is provided that is capable of biasing an amplifier transistor having a control terminal, a current-sink terminal, and a current-source terminal in order to control inter-modulation and linearize the output corresponding to radio frequency and microwave frequency ranges. Additionally, an embodiment of the present circuit is capable of dynamic power control. The transistor bias circuit according to the present invention utilizes a leakage current to alter the electrical characteristics of the amplifier transistor. The bias circuit comprises a bias transistor having a control terminal, a current-sink terminal, and a current-source terminal. Additionally, at least one DC input port, at least one resonator element, a diode element, and a resistive element is provided.

Abstract: A transistor bias circuit is provided that is capable of biasing an amplifier transistor having a control terminal, a current-sink terminal, and a current-source terminal in order to control inter-modulation and linearize the output corresponding to radio frequency and microwave frequency ranges. Additionally, an embodiment of the present circuit is capable of dynamic power control. The transistor bias circuit according to the present invention utilizes a leakage current to alter the electrical characteristics of the amplifier transistor. The bias circuit comprises a bias transistor having a control terminal, a current-sink terminal, and a current-source terminal. Additionally, at least one DC input port, at least one resonator element, a diode element, and a resistive element is provided.