Patents by Inventor Sang Woon Yang

Sang Woon Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10310817
    Abstract: An apparatus and method for modular multiplication. The modular multiplication apparatus includes a first operation unit for performing a first operation based on a structure of at least one of a serial multiplier and a serial squarer-based multiplier; a second operation unit for performing a second operation based on a structure of at least one of the serial multiplier and the serial squarer-based multiplier; an adder unit for outputting the sum of results of the first operation and the second operation, inputting an intermediate value stream to the first input unit, which calculates the product of the intermediate value stream and a zeta parameter, and outputting a High-Order Term as a result of Montgomery Modular Multiplication, wherein the first and second operation units output a result in digit-serial format in order from the least significant digit to the most significant digit.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: June 4, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yun-Koo Lee, Dong-Geon Lee, Min-Kyu Joo, Yoen-Cheol Lee, Sang-Woon Yang
  • Publication number: 20180181374
    Abstract: An apparatus and method for modular multiplication. The modular multiplication apparatus includes a first operation unit for performing a first operation based on a structure of at least one of a serial multiplier and a serial squarer-based multiplier; a second operation unit for performing a second operation based on a structure of at least one of the serial multiplier and the serial squarer-based multiplier; an adder unit for outputting the sum of results of the first operation and the second operation, inputting an intermediate value stream to the first input unit, which calculates the product of the intermediate value stream and a zeta parameter, and outputting a High-Order Term as a result of Montgomery Modular Multiplication, wherein the first and second operation units output a result in digit-serial format in order from the least significant digit to the most significant digit.
    Type: Application
    Filed: November 9, 2017
    Publication date: June 28, 2018
    Inventors: Yun-Koo LEE, Dong-Geon LEE, Min-Kyu JOO, Yoen-Cheol LEE, Sang-Woon YANG
  • Patent number: 9627690
    Abstract: A positive electrode composition for a rechargeable lithium battery includes a positive active material, a spherically shaped conductive material, and a sheet-shaped conductive material. The spherically shaped conductive material is included in an amount of about 1.1 to about 10 parts by weight based on 1 part by weight of the sheet-shaped conductive material. A positive electrode includes the positive electrode composition and a rechargeable lithium battery includes the positive electrode.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: April 18, 2017
    Assignee: Samsung SDI Co., Ltd.
    Inventors: In Kim, Eun-Jung Kim, Sang-Woon Yang, Young-Eun Kim, Jae-Kyung Kim
  • Publication number: 20160043403
    Abstract: A positive electrode composition for a rechargeable lithium battery includes a positive active material, a spherically shaped conductive material, and a sheet-shaped conductive material. The spherically shaped conductive material is included in an amount of about 1.1 to about 10 parts by weight based on 1 part by weight of the sheet-shaped conductive material. A positive electrode includes the positive electrode composition and a rechargeable lithium battery includes the positive electrode.
    Type: Application
    Filed: May 29, 2015
    Publication date: February 11, 2016
    Inventors: In Kim, Eun-Jung Kim, Sang-Woon Yang, Young-Eun Kim, Jae-Kyung Kim
  • Patent number: 8855309
    Abstract: An apparatus and method for providing a security service are provided. The apparatus for providing a security service includes a first block cipher and a second block cipher. The second block cipher is independent of the first block cipher, and is configured to be used as a random number generator when the first block cipher is used to perform encryption/decryption, and to be used to perform encryption/decryption when the first block cipher is used as a random number generator.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: October 7, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yun-Koo Lee, Jae-Heon Kim, Sang-Woon Yang, Jun-Young Son, Bong-Soo Lee
  • Patent number: 8621298
    Abstract: An apparatus for protecting against external attacks for a processor based on an ARM core and a method using the same are provided. A method for protecting against external attacks for a processor based on an ARM core in accordance with an embodiment of the present invention includes: setting up a register using a reset handler, which is executed first within a boot image; generating a control signal for protecting against external attacks using any one of an external debug request signal and an output signal of the register; and blocking a JTAG interface used for JTAG communication with the processor based on the ARM core according to the control signal for protecting against external attacks.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: December 31, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jun-Young Son, Yun-Koo Lee, Sang-Woon Yang, Bong-Soo Lee
  • Publication number: 20130329887
    Abstract: An apparatus and method for providing a security service are provided. The apparatus for providing a security service includes a first block cipher and a second block cipher. The second block cipher is independent of the first block cipher, and is configured to be used as a random number generator when the first block cipher is used to perform encryption/decryption, and to be used to perform encryption/decryption when the first block cipher is used as a random number generator.
    Type: Application
    Filed: November 19, 2012
    Publication date: December 12, 2013
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yun-Koo LEE, Jae-Heon KIM, Sang-Woon YANG, Jun-Young SON, Bong-Soo LEE
  • Patent number: 8555387
    Abstract: Provided are an apparatus and method using spatial and temporal quarantine expansion to prevent important information from being leaked due to attacks such as viruses, hacking, and the like.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: October 8, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yun Koo Lee, Sang Woon Yang, Jae Hwan Ahn, Joung Chul Ahn
  • Publication number: 20130166975
    Abstract: An apparatus for protecting against external attacks for a processor based on an ARM core and a method using the same are provided. A method for protecting against external attacks for a processor based on an ARM core in accordance with an embodiment of the present invention includes: setting up a register using a reset handler, which is executed first within a boot image; generating a control signal for protecting against external attacks using any one of an external debug request signal and an output signal of the register; and blocking a JTAG interface used for JTAG communication with the processor based on the ARM core according to the control signal for protecting against external attacks.
    Type: Application
    Filed: June 1, 2012
    Publication date: June 27, 2013
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jun-Young SON, Yun-Koo LEE, Sang-Woon YANG, Bong-Soo LEE
  • Publication number: 20120076294
    Abstract: Provided are an arithmetic method and apparatus for supporting Advanced Encryption Standard (AES) and Academy, Research Institute and Agency (ARIA) encryption/decryption functions. The apparatus includes: a key scheduler for generating a round key using an input key; and a round function calculator for generating encrypted/decrypted data using input data and the round key. Here, the round function calculator includes an integrated substitution layer and an integrated diffusion layer capable of performing both AES and ARIA algorithms.
    Type: Application
    Filed: December 6, 2011
    Publication date: March 29, 2012
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Bon Seok KOO, Gwon Ho RYU, Sang Woon YANG, Tae Joo CHANG
  • Patent number: 8094815
    Abstract: Provided are an arithmetic method and apparatus for supporting Advanced Encryption Standard (AES) and Academy, Research Institute and Agency (ARIA) encryption/decryption functions. The apparatus includes: a key scheduler for generating a round key using an input key; and a round function calculator for generating encrypted/decrypted data using input data and the round key. Here, the round function calculator includes an integrated substitution layer and an integrated diffusion layer capable of performing both AES and ARIA algorithms.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: January 10, 2012
    Assignee: Electronics andTelecommunications Research Institute
    Inventors: Bon Seok Koo, Gwon Ho Ryu, Sang Woon Yang, Tae Joo Chang
  • Publication number: 20100162397
    Abstract: Provided are an apparatus and method using spatial and temporal quarantine expansion to prevent important information from being leaked due to attacks such as viruses, hacking, and the like.
    Type: Application
    Filed: December 21, 2009
    Publication date: June 24, 2010
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yun Koo LEE, Sang Woon YANG, Jae Hwan AHN, Joung Chul AHN
  • Publication number: 20080112560
    Abstract: Provided are an arithmetic method and apparatus for supporting Advanced Encryption Standard (AES) and Academy, Research Institute and Agency (ARIA) encryption/decryption functions. The apparatus includes: a key scheduler for generating a round key using an input key; and a round function calculator for generating encrypted/decrypted data using input data and the round key. Here, the round function calculator includes an integrated substitution layer and an integrated diffusion layer capable of performing both AES and ARIA algorithms.
    Type: Application
    Filed: October 25, 2007
    Publication date: May 15, 2008
    Inventors: Bon Seok KOO, Gwon Ho RYU, Sang Woon YANG, Tae Joo CHANG