Abstract: A method is for operating a nonvolatile memory device, where the memory device includes a memory cell array and a page buffer block. The method includes loading program data into the page buffer block, loading random sequence data into the page buffer block, generating randomized data by executing a logic operation, such as a bit-wise XOR operation, in the page buffer circuit on the program data and the first random sequence data, and programming the randomized data into the memory cell array.

Abstract: Disclosed is an on-chip buffer program method for a data storage device which comprises a multi-bit memory device and a memory controller. The on-chip buffer program method includes measuring a performance of the data storage device, judging whether the measured performance satisfies a target performance of the data storage device, and selecting one of a plurality of scheduling manners as an on-chip buffer program scheduling manner of the data storage device according to the judgment result.

Abstract: A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation.

Abstract: A data storage device includes a multi-bit memory device including a memory cell array, the memory cell array including a first memory region and a second memory region, and a memory controller including a buffer memory and configured to control the multi-bit memory device. The memory controller is configured to control the multi-bit memory device to execute a buffer program operation in which data stored in the buffer memory is stored in the first memory region, and to control the multi-bit memory device to execute a main program operation in which the data stored in the first memory region is stored in the second memory region. The memory controller is further configured to generate parity data based upon the data stored to the first region, the parity data being copied from the first memory region to the second memory region via the main program operation.

Abstract: A method of programming memory cells (transistors) of a nonvolatile memory device from a first set of (previous) logic states to a second set of (final) logic states. The method includes applying program voltages to selected memory transistors; and applying a pre-verification voltage and a target verification voltage for verifying the current logic state of the selected memory transistors. The voltage interval between logic states of the second set of logic states is less than the voltage interval between logic states of the first set of logic states. A target verification voltage for verifying a first memory transistor is at one logic state of the second set is used as a pre-verification voltage for verifying that a second memory transistor to be programmed to higher logic state of the second set.

Abstract: A data storage device includes a non-volatile memory device including a memory cell array, where the memory cell array includes a first region and a second region, and a memory controller configured to judge whether a size of data externally provided according to a write request exceeds a reference size, and to control the non-volatile memory device according to a judgment result. When the externally provided data exceeds the reference size, the memory controller controls the non-volatile memory device such that a portion of the externally provided data is stored in the second region via a main program operation and such that a remainder of the externally provided data is stored in the first region via a buffer program operation.

Abstract: In one embodiment, the method for reading memory cells in an array of non-volatile memory cells includes reading data from a memory cell using a set of hard decision voltages and at least a first set of soft decision voltages based on a single read command.

Abstract: A data storage device includes a non-volatile memory device which includes a memory cell array; and a memory controller which includes a buffer memory and which controls the non-volatile memory device. The operating method of the data storage device includes storing data in the buffer memory according to an external request, and determining whether the data stored in the buffer memory is data accompanying a buffer program operation of the memory cell array. When the data stored in the buffer memory is data accompanying the buffer program operation, the method further includes determining whether a main program operation on the memory cell array is required, and when a main program operation on the memory cell array is required, determining a program pattern of the main program operation on the memory cell array. The method further includes issuing a set of commands for the main program operation on the memory cell array to the multi-bit memory device based on the determined program pattern.

Abstract: Memory devices include an array of non-volatile memory cells and a memory control circuit. The memory control circuit, which is electrically coupled to the array of non-volatile memory cells, includes a pseudo-random data coder/decoder circuit. This pseudo-random data coder/decoder circuit is configured to convert a first block of input data to be written into the memory device into a second block of data. This second block of data is encoded as a two-dimensional pseudo-random distribution of data values, which are more uniformly distributed relative to data values in the first block of input data. The memory control circuit is further configured to write the second block of data into the array of non-volatile memory cells during a plurality of page write operations.

Abstract: A nonvolatile memory includes a plurality of N-bit multi-level cell (MLC) memory cells and a controller. The plurality of N-bit MLC memory cells are for storing N pages of data, each of the MLC memory cells programmable into any one of 2N threshold voltage distributions, where N is a positive number.

Abstract: A nonvolatile memory device performs a program operation comprising applying a program pulse to selected memory cells, detecting a number of fail bits among the selected memory cells, the fail bits comprising failed program bits and disturbed inhibit bits, and determining a program completion status of the program operation based on the number of detected fail bits.

Abstract: A method is for operating a nonvolatile memory device, where the memory device includes a memory cell array and a page buffer block. The method includes loading program data into the page buffer block, loading random sequence data into the page buffer block, generating randomized data by executing a logic operation, such as a bit-wise XOR operation, in the page buffer circuit on the program data and the first random sequence data, and programming the randomized data into the memory cell array.