Patents by Inventor Sang-Youn Jo
Sang-Youn Jo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11963357Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes a conductive plate, a barrier conductive film extending along a surface of the conductive plate, a mold structure including a plurality of gate electrodes sequentially stacked on the barrier conductive film, a channel hole penetrating the mold structure to expose the barrier conductive film, an impurity pattern being in contact with the barrier conductive film, and formed in the channel hole, and a semiconductor pattern formed in the channel hole, extending from the impurity pattern along a side surface of the channel hole, and intersecting the plurality of gate electrodes.Type: GrantFiled: December 14, 2022Date of Patent: April 16, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kohji Kanamori, Seo-Goo Kang, Hyo Joon Ryu, Sang Youn Jo, Jee Hoon Han
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Patent number: 11942463Abstract: A semiconductor device includes a first substrate structure including a first substrate, gate electrodes stacked on the first substrate, and extended by different lengths to provide contact regions, cell contact plugs connected to the gate electrodes in the contact regions, and first bonding pads disposed on the cell contact plugs to be electrically connected to the cell contact plugs, respectively, and a second substrate structure, connected to the first substrate structure on the first substrate structure, and including a second substrate, circuit elements disposed on the second substrate, and a second bonding pad bonded to the first bonding pads, wherein, the contact regions include first regions having a first width and second regions, of which at least a portion overlaps the first bonding pads, and which have a second width greater than the first width, and the second width is greater than a width of the first bonding pad.Type: GrantFiled: April 28, 2023Date of Patent: March 26, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun Mog Park, Sang Youn Jo
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Publication number: 20240062808Abstract: A nonvolatile memory device includes a first lower interlayer insulation layer and a second lower interlayer insulation layer that are sequentially stacked in a first direction; a lower metal layer disposed in the first lower interlayer insulation layer; and a plurality of lower bonding metals disposed in the first lower interlayer insulation layer and the second lower interlayer insulation layer and spaced apart from each other in a second direction that intersects the first direction. An uppermost surface in the first direction of the lower metal layer is lower than an uppermost surface in the first direction of the plurality of lower bonding metals, and the lower metal layer is placed between the plurality of lower bonding metals.Type: ApplicationFiled: September 4, 2023Publication date: February 22, 2024Inventors: Kohji KANAMORI, Sang Youn JO, Jee Hoon HAN
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Patent number: 11769546Abstract: A nonvolatile memory device includes a first lower interlayer insulation layer and a second lower interlayer insulation layer that are sequentially stacked in a first direction; a lower metal layer disposed in the first lower interlayer insulation layer; and a plurality of lower bonding metals disposed in the first lower interlayer insulation layer and the second lower interlayer insulation layer and spaced apart from each other in a second direction that intersects the first direction. An uppermost surface in the first direction of the lower metal layer is lower than an uppermost surface in the first direction of the plurality of lower bonding metals, and the lower metal layer is placed between the plurality of lower bonding metals.Type: GrantFiled: September 2, 2021Date of Patent: September 26, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kohji Kanamori, Sang Youn Jo, Jee Hoon Han
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Publication number: 20230268333Abstract: A semiconductor device includes a first substrate structure including a first substrate, gate electrodes stacked on the first substrate, and extended by different lengths to provide contact regions, cell contact plugs connected to the gate electrodes in the contact regions, and first bonding pads disposed on the cell contact plugs to be electrically connected to the cell contact plugs, respectively, and a second substrate structure, connected to the first substrate structure on the first substrate structure, and including a second substrate, circuit elements disposed on the second substrate, and a second bonding pad bonded to the first bonding pads, wherein, the contact regions include first regions having a first width and second regions, of which at least a portion overlaps the first bonding pads, and which have a second width greater than the first width, and the second width is greater than a width of the first bonding pad.Type: ApplicationFiled: April 28, 2023Publication date: August 24, 2023Inventors: Hyun Mog PARK, Sang Youn JO
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Patent number: 11664362Abstract: A semiconductor device includes a first substrate structure including a first substrate, gate electrodes stacked on the first substrate, and extended by different lengths to provide contact regions, cell contact plugs connected to the gate electrodes in the contact regions, and first bonding pads disposed on the cell contact plugs to be electrically connected to the cell contact plugs, respectively, and a second substrate structure, connected to the first substrate structure on the first substrate structure, and including a second substrate, circuit elements disposed on the second substrate, and a second bonding pad bonded to the first bonding pads, wherein, the contact regions include first regions having a first width and second regions, of which at least a portion overlaps the first bonding pads, and which have a second width greater than the first width, and the second width is greater than a width of the at least one first bonding pad.Type: GrantFiled: March 7, 2022Date of Patent: May 30, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun Mog Park, Sang Youn Jo
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Publication number: 20230122331Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes a conductive plate, a barrier conductive film extending along a surface of the conductive plate, a mold structure including a plurality of gate electrodes sequentially stacked on the barrier conductive film, a channel hole penetrating the mold structure to expose the barrier conductive film, an impurity pattern being in contact with the barrier conductive film, and formed in the channel hole, and a semiconductor pattern formed in the channel hole, extending from the impurity pattern along a side surface of the channel hole, and intersecting the plurality of gate electrodes.Type: ApplicationFiled: December 14, 2022Publication date: April 20, 2023Inventors: KOHJI KANAMORI, SEO-GOO KANG, HYO JOON RYU, SANG YOUN JO, JEE HOON HAN
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Patent number: 11563028Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes a conductive plate, a barrier conductive film extending along a surface of the conductive plate, a mold structure including a plurality of gate electrodes sequentially stacked on the barrier conductive film, a channel hole penetrating the mold structure to expose the barrier conductive film, an impurity pattern being in contact with the barrier conductive film, and formed in the channel hole, and a semiconductor pattern formed in the channel hole, extending from the impurity pattern along a side surface of the channel hole, and intersecting the plurality of gate electrodes.Type: GrantFiled: September 28, 2020Date of Patent: January 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kohji Kanamori, Seo-Goo Kang, Hyo Joon Ryu, Sang Youn Jo, Jee Hoon Han
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Publication number: 20220189940Abstract: A semiconductor device includes a first substrate structure including a first substrate, gate electrodes stacked on the first substrate, and extended by different lengths to provide contact regions, cell contact plugs connected to the gate electrodes in the contact regions, and first bonding pads disposed on the cell contact plugs to be electrically connected to the cell contact plugs, respectively, and a second substrate structure, connected to the first substrate structure on the first substrate structure, and including a second substrate, circuit elements disposed on the second substrate, and a second bonding pad bonded to the first bonding pads, wherein, the contact regions include first regions having a first width and second regions, of which at least a portion overlaps the first bonding pads, and which have a second width greater than the first width, and the second width is greater than a width of the at least one first bonding pad.Type: ApplicationFiled: March 7, 2022Publication date: June 16, 2022Inventors: Hyun Mog PARK, Sang Youn JO
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Publication number: 20220101911Abstract: A nonvolatile memory device includes a first lower interlayer insulation layer and a second lower interlayer insulation layer that are sequentially stacked in a first direction; a lower metal layer disposed in the first lower interlayer insulation layer; and a plurality of lower bonding metals disposed in the first lower interlayer insulation layer and the second lower interlayer insulation layer and spaced apart from each other in a second direction that intersects the first direction. An uppermost surface in the first direction of the lower metal layer is lower than an uppermost surface in the first direction of the plurality of lower bonding metals, and the lower metal layer is placed between the plurality of lower bonding metals.Type: ApplicationFiled: September 2, 2021Publication date: March 31, 2022Inventors: KOHJI KANAMORI, Sang Youn JO, Jee Hoon HAN
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Patent number: 11270987Abstract: A semiconductor device includes a first substrate structure including a first substrate, gate electrodes stacked on the first substrate, and extended by different lengths to provide contact regions, cell contact plugs connected to the gate electrodes in the contact regions, and first bonding pads disposed on the cell contact plugs to be electrically connected to the cell contact plugs, respectively, and a second substrate structure, connected to the first substrate structure on the first substrate structure, and including a second substrate, circuit elements disposed on the second substrate, and a second bonding pad bonded to the first bonding pads, wherein, the contact regions include first regions having a first width and second regions, of which at least a portion overlaps the first bonding pads, and which have a second width greater than the first width, and the second width is greater than a width of the at least one first bonding pad.Type: GrantFiled: August 14, 2020Date of Patent: March 8, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun Mog Park, Sang Youn Jo
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Publication number: 20210296358Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes a conductive plate, a barrier conductive film extending along a surface of the conductive plate, a mold structure including a plurality of gate electrodes sequentially stacked on the barrier conductive film, a channel hole penetrating the mold structure to expose the barrier conductive film, an impurity pattern being in contact with the barrier conductive film, and formed in the channel hole, and a semiconductor pattern formed in the channel hole, extending from the impurity pattern along a side surface of the channel hole, and intersecting the plurality of gate electrodes.Type: ApplicationFiled: September 28, 2020Publication date: September 23, 2021Inventors: KOHJI KANAMORI, SEO-GOO KANG, HYO JOON RYU, SANG YOUN JO, JEE HOON HAN
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Publication number: 20200381413Abstract: A semiconductor device includes a first substrate structure including a first substrate, gate electrodes stacked on the first substrate, and extended by different lengths to provide contact regions, cell contact plugs connected to the gate electrodes in the contact regions, and first bonding pads disposed on the cell contact plugs to be electrically connected to the cell contact plugs, respectively, and a second substrate structure, connected to the first substrate structure on the first substrate structure, and including a second substrate, circuit elements disposed on the second substrate, and a second bonding pad bonded to the first bonding pads, wherein, the contact regions include first regions having a first width and second regions, of which at least a portion overlaps the first bonding pads, and which have a second width greater than the first width, and the second width is greater than a width of the at least one first bonding pad.Type: ApplicationFiled: August 14, 2020Publication date: December 3, 2020Inventors: Hyun Mog PARK, Sang Youn JO
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Patent number: 10748886Abstract: A semiconductor device includes a first substrate structure including a first substrate, gate electrodes stacked on the first substrate, and extended by different lengths to provide contact regions, cell contact plugs connected to the gate electrodes in the contact regions, and first bonding pads disposed on the cell contact plugs to be electrically connected to the cell contact plugs, respectively, and a second substrate structure, connected to the first substrate structure on the first substrate structure, and including a second substrate, circuit elements disposed on the second substrate, and a second bonding pad bonded to the first bonding pads, wherein, the contact regions include first regions having a first width and second regions, of which at least a portion overlaps the first bonding pads, and which have a second width greater than the first width, and the second width is greater than a width of the first bonding pad.Type: GrantFiled: May 16, 2019Date of Patent: August 18, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun Mog Park, Sang Youn Jo
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Publication number: 20200105735Abstract: A semiconductor device includes a first substrate structure including a first substrate, gate electrodes stacked on the first substrate, and extended by different lengths to provide contact regions, cell contact plugs connected to the gate electrodes in the contact regions, and first bonding pads disposed on the cell contact plugs to be electrically connected to the cell contact plugs, respectively, and a second substrate structure, connected to the first substrate structure on the first substrate structure, and including a second substrate, circuit elements disposed on the second substrate, and a second bonding pad bonded to the first bonding pads, wherein, the contact regions include first regions having a first width and second regions, of which at least a portion overlaps the first bonding pads, and which have a second width greater than the first width, and the second width is greater than a width of the first bonding pad.Type: ApplicationFiled: May 16, 2019Publication date: April 2, 2020Inventors: Hyun Mog PARK, Sang Youn JO
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Patent number: 9035396Abstract: In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.Type: GrantFiled: September 22, 2011Date of Patent: May 19, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung-ho Kwon, Sang-youn Jo, Jin-sook Choi, Chang-ki Hong, Bo-un Yoon, Hong-soo Kim, Se-rah Yun
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Publication number: 20120318567Abstract: A wiring structure includes a first plug extending through a first insulating interlayer on a substrate, a first wiring extending through a second insulating interlayer on the first insulating interlayer and the first wiring is electrically connected to the first plug, a diffusion barrier layer pattern on the first wiring and on the second insulating interlayer, a portion of the second insulating interlayer being free of being covered by the diffusion barrier layer pattern, a second plug extending through the diffusion barrier layer pattern, the second plug is in contact with the first wiring, and a second wiring electrically connected to the second plug.Type: ApplicationFiled: June 13, 2012Publication date: December 20, 2012Inventors: Jong-Hyun PARK, Jee-Yong KIM, Joon-Hee LEE, Jai-Hyuk SONG, Sang-Youn JO
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Patent number: 8227354Abstract: Provided is a method of forming patterns of a semiconductor device, whereby patterns having various widths can be simultaneously formed, and pattern density can be doubled by a double patterning process in a portion of the semiconductor device. In the method of forming patterns of a semiconductor device, a first mold mask pattern and a second mold mask patter having different widths are formed on a substrate. A pair of first spacers covering both sidewalls of the first mold mask pattern and a pair of second spacers covering both sidewalls of the second mold mask pattern are formed. The first mold mask pattern and the second mold mask pattern are removed, and a wide-width mask pattern covering the second spacer is formed. A lower layer is etched using the first spacers, the second spacers, and the wide-width mask pattern as an etch mask.Type: GrantFiled: June 9, 2009Date of Patent: July 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Bong-cheol Kim, Dae-youp Lee, Sang-youn Jo, Ja-min Koo, Byeong-hwan Son, Jang-hwan Jeong
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Publication number: 20120028435Abstract: In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.Type: ApplicationFiled: September 22, 2011Publication date: February 2, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung-ho Kwon, Sang-youn Jo, Jin-sook Choi, Chang-ki Hong, Bo-un Yoon, Hong-soo Kim, Se-rah Yun
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Patent number: 8053845Abstract: In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.Type: GrantFiled: November 7, 2008Date of Patent: November 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Byoung-ho Kwon, Sang-youn Jo, Jin-sook Choi, Chang-ki Hong, Bo-un Yoon, Hong-soo Kim, Se-rah Yun