Patents by Inventor Sanh D. Tang

Sanh D. Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods, devices, and systems relating to memory cells having a floating body
    Patent number: 7929343
    Abstract: Methods, devices, and systems are disclosed relating to a memory cell having a floating body. A memory cell includes a transistor comprising a drain and a source each formed in silicon and a gate positioned between the drain and the source. The memory cell may further include a bias gate recessed into the silicon and positioned between an isolation region and the transistor. In addition, the bias gate may be configured to be operably coupled to a bias voltage. The memory cell may also include a floating body within the silicon. The floating body may include a first portion adjacent the source and the drain and vertically offset from the bias gate and a second portion coupled to the first portion. Moreover, the bias gate may be formed adjacent to the second portion.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: April 19, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Sanh D. Tang
  • Methods of Forming Field Effect Transistors on Substrates
    Publication number: 20110086476
    Abstract: The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect transistor on a substrate, where the field effect transistor comprises a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region. Such implementation includes conducting a dopant activation anneal of the pair of source/drain regions prior to depositing material from which a conductive portion of the transistor gate is made. Other aspects and implementations are contemplated.
    Type: Application
    Filed: December 15, 2010
    Publication date: April 14, 2011
    Applicant: Micron Technology, Inc.
    Inventors: Robert J. Hanson, Sanh D. Tang
  • Methods Of Fabricating An Access Transistor Having A Polysilicon-Comprising Plug On Individual Of Opposing Sides Of Gate Material
    Publication number: 20110081755
    Abstract: Fabrication methods for gate transistors in integrated circuit devices enable the formation of recessed access device structures or FinFET structures having P-type workfunctions. The fabrication methods also provide for the formation of access transistor gates of an access device following formation of the periphery transistor gates. Access devices and systems including same are also disclosed.
    Type: Application
    Filed: December 6, 2010
    Publication date: April 7, 2011
    Applicant: Micron Technology, Inc.
    Inventors: Gordon A. Haller, Sanh D. Tang
  • Methods of forming recessed access devices associated with semiconductor constructions
    Patent number: 7897460
    Abstract: The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: March 1, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Kunal R. Parekh, Suraj Mathew, Jigish D. Trivedi, John K. Zahurak, Sanh D. Tang
  • Semiconductor Constructions and Transistors, and Methods of Forming Semiconductor Constructions and Transistors
    Publication number: 20110012182
    Abstract: The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.
    Type: Application
    Filed: September 27, 2010
    Publication date: January 20, 2011
    Applicant: Micron Technology Inc.
    Inventors: Sanh D. TANG, Gordon HALLER, Kris K. BROWN, Tuman Earl ALLEN, III
  • Transistor gate forming methods and transistor structures
    Patent number: 7867845
    Abstract: A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: January 11, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Gordon A. Haller, Prashant Raghu, Ravi Iyer
  • Methods of forming field effect transistors on substrates
    Patent number: 7867851
    Abstract: The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect transistor on a substrate, where the field effect transistor comprises a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region. Such implementation includes conducting a dopant activation anneal of the pair of source/drain regions prior to depositing material from which a conductive portion of the transistor gate is made. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: January 11, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Robert J. Hanson, Sanh D. Tang
  • Methods of fabricating an access transistor for an integrated circuit device, methods of fabricating periphery transistors and access transistors, and methods of fabricating an access device comprising access transistors in an access circuitry region and peripheral transistors in a peripheral circuitry region spaced from the access circuitry region
    Patent number: 7858471
    Abstract: Fabrication methods for gate transistors in integrated circuit devices enable the formation of recessed access device structures or FinFET structures having P-type workfunctions. The fabrication methods also provide for the formation of access transistor gates of an access device following formation of the periphery transistor gates. Access devices and systems including same are also disclosed.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: December 28, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Gordon A. Haller, Sanh D. Tang
  • Transistors
    Patent number: 7825462
    Abstract: The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: November 2, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Gordon Haller, Kris K. Brown, Tuman Earl Allen, III
  • Memory Arrays and Methods of Fabricating Memory Arrays
    Publication number: 20100273303
    Abstract: A memory array includes a plurality of memory cells formed on a semiconductor substrate. Individual of the memory cells include first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions. The gates of the first and second field effect transistors are hard wired together. A conductive data line is hard wired to two of the source/drain regions. A charge storage device is hard wired to at least one of the source/drain regions other than the two. Other aspects and implementations are contemplated, including methods of fabricating memory arrays.
    Type: Application
    Filed: July 1, 2010
    Publication date: October 28, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Gordon A. Haller, Sanh D. Tang
  • METHODS, DEVICES, AND SYSTEMS RELATING TO MEMORY CELLS HAVING A FLOATING BODY
    Publication number: 20100254186
    Abstract: Methods, devices, and systems are disclosed relating to a memory cell having a floating body. A memory cell includes a transistor comprising a drain and a source each formed in silicon and a gate positioned between the drain and the source. The memory cell may further include a bias gate recessed into the silicon and positioned between an isolation region and the transistor. In addition, the bias gate may be configured to be operably coupled to a bias voltage. The memory cell may also include a floating body within the silicon. The floating body may include a first portion adjacent the source and the drain and vertically offset from the bias gate and a second portion coupled to the first portion. Moreover, the bias gate may be formed adjacent to the second portion.
    Type: Application
    Filed: April 7, 2009
    Publication date: October 7, 2010
    Applicant: Micron Technology, Inc.
    Inventor: Sanh D. Tang
  • FIN STRUCTURES AND METHODS OF FABRICATING FIN STRUCTURES
    Publication number: 20100252886
    Abstract: There is provided fin structures and methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins.
    Type: Application
    Filed: June 7, 2010
    Publication date: October 7, 2010
    Applicant: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Gordon Haller
  • METHODS, DEVICES, AND SYSTEMS RELATING TO A MEMORY CELL HAVING A FLOATING BODY
    Publication number: 20100246285
    Abstract: Methods, devices, and systems are disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer and including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage and extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell includes a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.
    Type: Application
    Filed: March 24, 2009
    Publication date: September 30, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Sanh D. Tang, Mike N. Nguyen
  • Memory arrays and methods of fabricating memory arrays
    Patent number: 7772632
    Abstract: A memory array includes a plurality of memory cells formed on a semiconductor substrate. Individual of the memory cells include first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions. The gates of the first and second field effect transistors are hard wired together. A conductive data line is hard wired to two of the source/drain regions. A charge storage device is hard wired to at least one of the source/drain regions other than the two. Other aspects and implementations are contemplated, including methods of fabricating memory arrays.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: August 10, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Gordon A. Haller, Sanh D. Tang
  • System and method for fabricating a fin field effect transistor
    Patent number: 7745319
    Abstract: There is provided a system and method for fabricating a fin field effect transistor. More specifically, in one embodiment, there is provided a method comprising depositing a layer of nitride on a substrate, applying a photolithographic mask on the layer of nitride to define a location of a wall, etching the layer of nitride to create the wall, removing the photolithographic mask, depositing a spacer layer adjacent to the wall, etching the spacer layer to create a spacer adjacent to the wall, wherein the spacer and the wall cover a first portion of the substrate, and etching a second portion of the substrate not covered by the spacer to create a trench.
    Type: Grant
    Filed: August 22, 2006
    Date of Patent: June 29, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Gordon Haller
  • Integrated circuits
    Patent number: 7687857
    Abstract: Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and comprises a gate, a channel region, and a pair of source/drain regions. In one implementation, one of the source/drain regions is formed in the semiconductor material, and the other of the source/drain regions is formed in the bulk semiconductive material. In one implementation, the electrically insulative material extends from beneath one of the source/drain regions to beneath only a portion of the channel region. Other aspects and implementations, including methodical aspects, are disclosed.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: March 30, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Gordon Haller
  • Transistor structures
    Patent number: 7659560
    Abstract: A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: February 9, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Gordon A. Haller, Prashant Raghu, Ravi Iyer
  • One Transistor Memory Cell with Bias Gate
    Publication number: 20090311845
    Abstract: One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.
    Type: Application
    Filed: August 7, 2009
    Publication date: December 17, 2009
    Applicant: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Gordon Haller, Daniel H. Doyle
  • One-transistor memory cell with bias gate
    Patent number: 7589995
    Abstract: One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: September 15, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Gordon Haller, Daniel H. Doyle
  • VERTICAL WRAP-AROUND-GATE FIELD-EFFECT-TRANSISTOR FOR HIGH DENSITY, LOW VOLTAGE LOGIC AND MEMORY ARRAY
    Publication number: 20090207649
    Abstract: A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.
    Type: Application
    Filed: April 2, 2009
    Publication date: August 20, 2009
    Inventors: Sanh D. Tang, Robert J. Burke, Anand Srinivasan