Patents by Inventor Saniya Rathod

Saniya Rathod has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220189974
    Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.
    Type: Application
    Filed: March 8, 2022
    Publication date: June 16, 2022
    Inventors: Jun Fang, Fei Wang, Saniya Rathod, Rutuparna Narulkar, Matthew Park, Matthew J. King
  • Patent number: 11282845
    Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jun Fang, Fei Wang, Saniya Rathod, Rutuparna Narulkar, Matthew Park, Matthew J. King
  • Patent number: 10762939
    Abstract: Computer memory technology is disclosed. In one example, a method for isolating computer memory blocks in a memory array from one another can include forming an opening between adjacent blocks of memory structures. The method can also include forming a protective liner layer on at least the memory structures. The method can further include disposing isolating material in the opening and on the protective liner layer. The method can even further include removing the isolating material on the protective liner layer. The method can additionally include removing the protective liner layer on the memory structures. Associated devices and systems are also disclosed.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Christopher J. Larsen, David A. Daycock, Qian Tao, Saniya Rathod, Devesh K. Datta, Srivardhan Gowda, Rithu K. Bhonsle
  • Publication number: 20190067306
    Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.
    Type: Application
    Filed: August 24, 2017
    Publication date: February 28, 2019
    Inventors: Jun Fang, Fei Wang, Saniya Rathod, Rutuparna Narulkar, Matthew Park, Matthew J. King
  • Publication number: 20190005996
    Abstract: Computer memory technology is disclosed. In one example, a method for isolating computer memory blocks in a memory array from one another can include forming an opening between adjacent blocks of memory structures. The method can also include forming a protective liner layer on at least the memory structures. The method can further include disposing isolating material in the opening and on the protective liner layer. The method can even further include removing the isolating material on the protective liner layer. The method can additionally include removing the protective liner layer on the memory structures. Associated devices and systems are also disclosed.
    Type: Application
    Filed: July 1, 2017
    Publication date: January 3, 2019
    Applicant: Intel Corporation
    Inventors: Christopher J. Larsen, David A. Daycock, Qian Tao, Saniya Rathod, Devesh K. Datta, Srivardhan Gowda, Rithu K. Bhonsle